📄 mcu8951.fit.eqn
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--NB1_L_INTA is CPU8051C1:inst|MCU80512:inst3|m3s019bo:U11|L_INTA at LCFF_X17_Y4_N25
NB1_L_INTA = DFFEAS(NB1L147, GLOBAL(G1L1), RST, , , , , !K1_CLEAR, );
--NC1_ram_block3a8 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|ram_block3a8 at M4K_X23_Y6
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 8, Port B Logical Depth: 8192, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NC1_ram_block3a8_PORT_A_data_in = VCC;
NC1_ram_block3a8_PORT_A_data_in_reg = DFFE(NC1_ram_block3a8_PORT_A_data_in, NC1_ram_block3a8_clock_0, , , NC1_ram_block3a8_clock_enable_0);
NC1_ram_block3a8_PORT_B_data_in = PC2_ram_rom_data_reg[0];
NC1_ram_block3a8_PORT_B_data_in_reg = DFFE(NC1_ram_block3a8_PORT_B_data_in, NC1_ram_block3a8_clock_1, , , NC1_ram_block3a8_clock_enable_1);
NC1_ram_block3a8_PORT_A_address = BUS(KB1_PROGRAM_ADDR[0], KB1_PROGRAM_ADDR[1], KB1_PROGRAM_ADDR[2], KB1_PROGRAM_ADDR[3], KB1_PROGRAM_ADDR[4], KB1_PROGRAM_ADDR[5], KB1_PROGRAM_ADDR[6], KB1_PROGRAM_ADDR[7], KB1_PROGRAM_ADDR[8], KB1_PROGRAM_ADDR[9], KB1_PROGRAM_ADDR[10], KB1_PROGRAM_ADDR[11]);
NC1_ram_block3a8_PORT_A_address_reg = DFFE(NC1_ram_block3a8_PORT_A_address, NC1_ram_block3a8_clock_0, , , NC1_ram_block3a8_clock_enable_0);
NC1_ram_block3a8_PORT_B_address = BUS(PC2_ram_rom_addr_reg[0], PC2_ram_rom_addr_reg[1], PC2_ram_rom_addr_reg[2], PC2_ram_rom_addr_reg[3], PC2_ram_rom_addr_reg[4], PC2_ram_rom_addr_reg[5], PC2_ram_rom_addr_reg[6], PC2_ram_rom_addr_reg[7], PC2_ram_rom_addr_reg[8], PC2_ram_rom_addr_reg[9], PC2_ram_rom_addr_reg[10], PC2_ram_rom_addr_reg[11]);
NC1_ram_block3a8_PORT_B_address_reg = DFFE(NC1_ram_block3a8_PORT_B_address, NC1_ram_block3a8_clock_1, , , NC1_ram_block3a8_clock_enable_1);
NC1_ram_block3a8_PORT_A_write_enable = GND;
NC1_ram_block3a8_PORT_A_write_enable_reg = DFFE(NC1_ram_block3a8_PORT_A_write_enable, NC1_ram_block3a8_clock_0, , , NC1_ram_block3a8_clock_enable_0);
NC1_ram_block3a8_PORT_B_write_enable = QC2L2;
NC1_ram_block3a8_PORT_B_write_enable_reg = DFFE(NC1_ram_block3a8_PORT_B_write_enable, NC1_ram_block3a8_clock_1, , , NC1_ram_block3a8_clock_enable_1);
NC1_ram_block3a8_clock_0 = GLOBAL(G1L1);
NC1_ram_block3a8_clock_1 = GLOBAL(A1L6);
NC1_ram_block3a8_clock_enable_0 = KB1_PROGRAM_ADDR[12];
NC1_ram_block3a8_clock_enable_1 = PC2_ram_rom_addr_reg[12];
NC1_ram_block3a8_PORT_A_data_out = MEMORY(NC1_ram_block3a8_PORT_A_data_in_reg, NC1_ram_block3a8_PORT_B_data_in_reg, NC1_ram_block3a8_PORT_A_address_reg, NC1_ram_block3a8_PORT_B_address_reg, NC1_ram_block3a8_PORT_A_write_enable_reg, NC1_ram_block3a8_PORT_B_write_enable_reg, , , NC1_ram_block3a8_clock_0, NC1_ram_block3a8_clock_1, NC1_ram_block3a8_clock_enable_0, NC1_ram_block3a8_clock_enable_1, , );
NC1_ram_block3a8 = NC1_ram_block3a8_PORT_A_data_out[0];
--NC1M293 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|ram_block3a8~PORTBDATAOUT0 at M4K_X23_Y6
NC1M293_PORT_A_data_in = VCC;
NC1M293_PORT_A_data_in_reg = DFFE(NC1M293_PORT_A_data_in, NC1M293_clock_0, , , NC1M293_clock_enable_0);
NC1M293_PORT_B_data_in = PC2_ram_rom_data_reg[0];
NC1M293_PORT_B_data_in_reg = DFFE(NC1M293_PORT_B_data_in, NC1M293_clock_1, , , NC1M293_clock_enable_1);
NC1M293_PORT_A_address = BUS(KB1_PROGRAM_ADDR[0], KB1_PROGRAM_ADDR[1], KB1_PROGRAM_ADDR[2], KB1_PROGRAM_ADDR[3], KB1_PROGRAM_ADDR[4], KB1_PROGRAM_ADDR[5], KB1_PROGRAM_ADDR[6], KB1_PROGRAM_ADDR[7], KB1_PROGRAM_ADDR[8], KB1_PROGRAM_ADDR[9], KB1_PROGRAM_ADDR[10], KB1_PROGRAM_ADDR[11]);
NC1M293_PORT_A_address_reg = DFFE(NC1M293_PORT_A_address, NC1M293_clock_0, , , NC1M293_clock_enable_0);
NC1M293_PORT_B_address = BUS(PC2_ram_rom_addr_reg[0], PC2_ram_rom_addr_reg[1], PC2_ram_rom_addr_reg[2], PC2_ram_rom_addr_reg[3], PC2_ram_rom_addr_reg[4], PC2_ram_rom_addr_reg[5], PC2_ram_rom_addr_reg[6], PC2_ram_rom_addr_reg[7], PC2_ram_rom_addr_reg[8], PC2_ram_rom_addr_reg[9], PC2_ram_rom_addr_reg[10], PC2_ram_rom_addr_reg[11]);
NC1M293_PORT_B_address_reg = DFFE(NC1M293_PORT_B_address, NC1M293_clock_1, , , NC1M293_clock_enable_1);
NC1M293_PORT_A_write_enable = GND;
NC1M293_PORT_A_write_enable_reg = DFFE(NC1M293_PORT_A_write_enable, NC1M293_clock_0, , , NC1M293_clock_enable_0);
NC1M293_PORT_B_write_enable = QC2L2;
NC1M293_PORT_B_write_enable_reg = DFFE(NC1M293_PORT_B_write_enable, NC1M293_clock_1, , , NC1M293_clock_enable_1);
NC1M293_clock_0 = GLOBAL(G1L1);
NC1M293_clock_1 = GLOBAL(A1L6);
NC1M293_clock_enable_0 = KB1_PROGRAM_ADDR[12];
NC1M293_clock_enable_1 = PC2_ram_rom_addr_reg[12];
NC1M293_PORT_B_data_out = MEMORY(NC1M293_PORT_A_data_in_reg, NC1M293_PORT_B_data_in_reg, NC1M293_PORT_A_address_reg, NC1M293_PORT_B_address_reg, NC1M293_PORT_A_write_enable_reg, NC1M293_PORT_B_write_enable_reg, , , NC1M293_clock_0, NC1M293_clock_1, NC1M293_clock_enable_0, NC1M293_clock_enable_1, , );
NC1M293 = NC1M293_PORT_B_data_out[0];
--NC1_ram_block3a0 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|ram_block3a0 at M4K_X23_Y7
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 8, Port B Logical Depth: 8192, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NC1_ram_block3a0_PORT_A_data_in = VCC;
NC1_ram_block3a0_PORT_A_data_in_reg = DFFE(NC1_ram_block3a0_PORT_A_data_in, NC1_ram_block3a0_clock_0, , , NC1_ram_block3a0_clock_enable_0);
NC1_ram_block3a0_PORT_B_data_in = PC2_ram_rom_data_reg[0];
NC1_ram_block3a0_PORT_B_data_in_reg = DFFE(NC1_ram_block3a0_PORT_B_data_in, NC1_ram_block3a0_clock_1, , , NC1_ram_block3a0_clock_enable_1);
NC1_ram_block3a0_PORT_A_address = BUS(KB1_PROGRAM_ADDR[0], KB1_PROGRAM_ADDR[1], KB1_PROGRAM_ADDR[2], KB1_PROGRAM_ADDR[3], KB1_PROGRAM_ADDR[4], KB1_PROGRAM_ADDR[5], KB1_PROGRAM_ADDR[6], KB1_PROGRAM_ADDR[7], KB1_PROGRAM_ADDR[8], KB1_PROGRAM_ADDR[9], KB1_PROGRAM_ADDR[10], KB1_PROGRAM_ADDR[11]);
NC1_ram_block3a0_PORT_A_address_reg = DFFE(NC1_ram_block3a0_PORT_A_address, NC1_ram_block3a0_clock_0, , , NC1_ram_block3a0_clock_enable_0);
NC1_ram_block3a0_PORT_B_address = BUS(PC2_ram_rom_addr_reg[0], PC2_ram_rom_addr_reg[1], PC2_ram_rom_addr_reg[2], PC2_ram_rom_addr_reg[3], PC2_ram_rom_addr_reg[4], PC2_ram_rom_addr_reg[5], PC2_ram_rom_addr_reg[6], PC2_ram_rom_addr_reg[7], PC2_ram_rom_addr_reg[8], PC2_ram_rom_addr_reg[9], PC2_ram_rom_addr_reg[10], PC2_ram_rom_addr_reg[11]);
NC1_ram_block3a0_PORT_B_address_reg = DFFE(NC1_ram_block3a0_PORT_B_address, NC1_ram_block3a0_clock_1, , , NC1_ram_block3a0_clock_enable_1);
NC1_ram_block3a0_PORT_A_write_enable = GND;
NC1_ram_block3a0_PORT_A_write_enable_reg = DFFE(NC1_ram_block3a0_PORT_A_write_enable, NC1_ram_block3a0_clock_0, , , NC1_ram_block3a0_clock_enable_0);
NC1_ram_block3a0_PORT_B_write_enable = QC2L1;
NC1_ram_block3a0_PORT_B_write_enable_reg = DFFE(NC1_ram_block3a0_PORT_B_write_enable, NC1_ram_block3a0_clock_1, , , NC1_ram_block3a0_clock_enable_1);
NC1_ram_block3a0_clock_0 = GLOBAL(G1L1);
NC1_ram_block3a0_clock_1 = GLOBAL(A1L6);
NC1_ram_block3a0_clock_enable_0 = !KB1_PROGRAM_ADDR[12];
NC1_ram_block3a0_clock_enable_1 = !PC2_ram_rom_addr_reg[12];
NC1_ram_block3a0_PORT_A_data_out = MEMORY(NC1_ram_block3a0_PORT_A_data_in_reg, NC1_ram_block3a0_PORT_B_data_in_reg, NC1_ram_block3a0_PORT_A_address_reg, NC1_ram_block3a0_PORT_B_address_reg, NC1_ram_block3a0_PORT_A_write_enable_reg, NC1_ram_block3a0_PORT_B_write_enable_reg, , , NC1_ram_block3a0_clock_0, NC1_ram_block3a0_clock_1, NC1_ram_block3a0_clock_enable_0, NC1_ram_block3a0_clock_enable_1, , );
NC1_ram_block3a0 = NC1_ram_block3a0_PORT_A_data_out[0];
--NC1M37 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|ram_block3a0~PORTBDATAOUT0 at M4K_X23_Y7
NC1M37_PORT_A_data_in = VCC;
NC1M37_PORT_A_data_in_reg = DFFE(NC1M37_PORT_A_data_in, NC1M37_clock_0, , , NC1M37_clock_enable_0);
NC1M37_PORT_B_data_in = PC2_ram_rom_data_reg[0];
NC1M37_PORT_B_data_in_reg = DFFE(NC1M37_PORT_B_data_in, NC1M37_clock_1, , , NC1M37_clock_enable_1);
NC1M37_PORT_A_address = BUS(KB1_PROGRAM_ADDR[0], KB1_PROGRAM_ADDR[1], KB1_PROGRAM_ADDR[2], KB1_PROGRAM_ADDR[3], KB1_PROGRAM_ADDR[4], KB1_PROGRAM_ADDR[5], KB1_PROGRAM_ADDR[6], KB1_PROGRAM_ADDR[7], KB1_PROGRAM_ADDR[8], KB1_PROGRAM_ADDR[9], KB1_PROGRAM_ADDR[10], KB1_PROGRAM_ADDR[11]);
NC1M37_PORT_A_address_reg = DFFE(NC1M37_PORT_A_address, NC1M37_clock_0, , , NC1M37_clock_enable_0);
NC1M37_PORT_B_address = BUS(PC2_ram_rom_addr_reg[0], PC2_ram_rom_addr_reg[1], PC2_ram_rom_addr_reg[2], PC2_ram_rom_addr_reg[3], PC2_ram_rom_addr_reg[4], PC2_ram_rom_addr_reg[5], PC2_ram_rom_addr_reg[6], PC2_ram_rom_addr_reg[7], PC2_ram_rom_addr_reg[8], PC2_ram_rom_addr_reg[9], PC2_ram_rom_addr_reg[10], PC2_ram_rom_addr_reg[11]);
NC1M37_PORT_B_address_reg = DFFE(NC1M37_PORT_B_address, NC1M37_clock_1, , , NC1M37_clock_enable_1);
NC1M37_PORT_A_write_enable = GND;
NC1M37_PORT_A_write_enable_reg = DFFE(NC1M37_PORT_A_write_enable, NC1M37_clock_0, , , NC1M37_clock_enable_0);
NC1M37_PORT_B_write_enable = QC2L1;
NC1M37_PORT_B_write_enable_reg = DFFE(NC1M37_PORT_B_write_enable, NC1M37_clock_1, , , NC1M37_clock_enable_1);
NC1M37_clock_0 = GLOBAL(G1L1);
NC1M37_clock_1 = GLOBAL(A1L6);
NC1M37_clock_enable_0 = !KB1_PROGRAM_ADDR[12];
NC1M37_clock_enable_1 = !PC2_ram_rom_addr_reg[12];
NC1M37_PORT_B_data_out = MEMORY(NC1M37_PORT_A_data_in_reg, NC1M37_PORT_B_data_in_reg, NC1M37_PORT_A_address_reg, NC1M37_PORT_B_address_reg, NC1M37_PORT_A_write_enable_reg, NC1M37_PORT_B_write_enable_reg, , , NC1M37_clock_0, NC1M37_clock_1, NC1M37_clock_enable_0, NC1M37_clock_enable_1, , );
NC1M37 = NC1M37_PORT_B_data_out[0];
--NC1_address_reg_a[0] is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|address_reg_a[0] at LCFF_X22_Y6_N21
NC1_address_reg_a[0] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(G1L1), , , , KB1_PROGRAM_ADDR[12], , , VCC);
--RC1L1 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|mux_hib:mux6|result_node[0]~96 at LCCOMB_X22_Y6_N12
RC1L1 = NC1_address_reg_a[0] & NC1_ram_block3a8 # !NC1_address_reg_a[0] & (NC1_ram_block3a0);
--BB1_safe_q[5] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter6:inst17|lpm_counter:lpm_counter_component|cntr_dtd:auto_generated|safe_q[5] at LCFF_X7_Y2_N27
BB1_safe_q[5] = DFFEAS(BB1L23, J2L25, , , , , , J2L24, );
--BB1_safe_q[2] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter6:inst17|lpm_counter:lpm_counter_component|cntr_dtd:auto_generated|safe_q[2] at LCFF_X7_Y2_N21
BB1_safe_q[2] = DFFEAS(BB1L11, J2L25, , , , , , J2L24, );
--BB1_safe_q[3] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter6:inst17|lpm_counter:lpm_counter_component|cntr_dtd:auto_generated|safe_q[3] at LCFF_X7_Y2_N23
BB1_safe_q[3] = DFFEAS(BB1L15, J2L25, , , , , , J2L24, );
--BB1_safe_q[4] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter6:inst17|lpm_counter:lpm_counter_component|cntr_dtd:auto_generated|safe_q[4] at LCFF_X7_Y2_N25
BB1_safe_q[4] = DFFEAS(BB1L19, J2L25, , , , , , J2L24, );
--Z1L1 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|cmp_6:inst3|lpm_compare:lpm_compare_component|cmpr_s4h:auto_generated|aleb~21 at LCCOMB_X7_Y2_N0
Z1L1 = BB1_safe_q[5] # BB1_safe_q[4] & (BB1_safe_q[3] # BB1_safe_q[2]);
--MB1_L_EXPMEM is CPU8051C1:inst|MCU80512:inst3|m3s018bo:U10|L_EXPMEM at LCFF_X18_Y8_N21
MB1_L_EXPMEM = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(G1L1), RST, , CB1_LDV2CK2, KB1_EXT_PROG_EN, , , VCC);
--K1L180 is CPU8051C1:inst|MCU80512:inst3|muxiromd~45 at LCCOMB_X18_Y8_N8
K1L180 = K1L98 & CB1_STATD[3] & (EB1L4 # !UB1L46);
--K1L179 is CPU8051C1:inst|MCU80512:inst3|muxiromd~1 at LCCOMB_X18_Y8_N20
K1L179 = K1L180 # MB1_L_EXPMEM;
--K1L74 is CPU8051C1:inst|MCU80512:inst3|IROMD[0]~863 at LCCOMB_X15_Y10_N24
K1L74 = K1L179 & S90 # !K1L179 & (RC1L1 & Z1L1);
--QB1L16 is CPU8051C1:inst|MCU80512:inst3|m3s025bo:U14|OPC[0]~ICOMBOUT at LCCOMB_X18_Y10_N12
QB1L16 = !NB1_L_INTA & K1L74;
--QB1_L_OPLOAD is CPU8051C1:inst|MCU80512:inst3|m3s025bo:U14|L_OPLOAD at LCFF_X18_Y5_N27
QB1_L_OPLOAD = DFFEAS(QB1L7, GLOBAL(G1L1), , , , , , , );
--QB1L54 is CPU8051C1:inst|MCU80512:inst3|m3s025bo:U14|dat_lat~23 at LCCOMB_X18_Y8_N2
QB1L54 = CB1_LDV2CK2 & QB1_L_OPLOAD & CB1_STATD[1];
--NC1_ram_block3a9 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|ram_block3a9 at M4K_X11_Y7
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 8, Port B Logical Depth: 8192, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NC1_ram_block3a9_PORT_A_data_in = VCC;
NC1_ram_block3a9_PORT_A_data_in_reg = DFFE(NC1_ram_block3a9_PORT_A_data_in, NC1_ram_block3a9_clock_0, , , NC1_ram_block3a9_clock_enable_0);
NC1_ram_block3a9_PORT_B_data_in = PC2_ram_rom_data_reg[1];
NC1_ram_block3a9_PORT_B_data_in_reg = DFFE(NC1_ram_block3a9_PORT_B_data_in, NC1_ram_block3a9_clock_1, , , NC1_ram_block3a9_clock_enable_1);
NC1_ram_block3a9_PORT_A_address = BUS(KB1_PROGRAM_ADDR[0], KB1_PROGRAM_ADDR[1], KB1_PROGRAM_ADDR[2], KB1_PROGRAM_ADDR[3], KB1_PROGRAM_ADDR[4], KB1_PROGRAM_ADDR[5], KB1_PROGRAM_ADDR[6], KB1_PROGRAM_ADDR[7], KB1_PROGRAM_ADDR[8], KB1_PROGRAM_ADDR[9], KB1_PROGRAM_ADDR[10], KB1_PROGRAM_ADDR[11]);
NC1_ram_block3a9_PORT_A_address_reg = DFFE(NC1_ram_block3a9_PORT_A_address, NC1_ram_block3a9_clock_0, , , NC1_ram_block3a9_clock_enable_0);
NC1_ram_block3a9_PORT_B_address = BUS(PC2_ram_rom_addr_reg[0], PC2_ram_rom_addr_reg[1], PC2_ram_rom_addr_reg[2], PC2_ram_rom_addr_reg[3], PC2_ram_rom_addr_reg[4], PC2_ram_rom_addr_reg[5], PC2_ram_rom_addr_reg[6], PC2_ram_rom_addr_reg[7], PC2_ram_rom_addr_reg[8], PC2_ram_rom_addr_reg[9], PC2_ram_rom_addr_reg[10], PC2_ram_rom_addr_reg[11]);
NC1_ram_block3a9_PORT_B_address_reg = DFFE(NC1_ram_block3a9_PORT_B_address, NC1_ram_block3a9_clock_1, , , NC1_ram_block3a9_clock_enable_1);
NC1_ram_block3a9_PORT_A_write_enable = GND;
NC1_ram_block3a9_PORT_A_write_enable_reg = DFFE(NC1_ram_block3a9_PORT_A_write_enable, NC1_ram_block3a9_clock_0, , , NC1_ram_block3a9_clock_enable_0);
NC1_ram_block3a9_PORT_B_write_enable = QC2L2;
NC1_ram_block3a9_PORT_B_write_enable_reg = DFFE(NC1_ram_block3a9_PORT_B_write_enable, NC1_ram_block3a9_clock_1, , , NC1_ram_block3a9_clock_enable_1);
NC1_ram_block3a9_clock_0 = GLOBAL(G1L1);
NC1_ram_block3a9_clock_1 = GLOBAL(A1L6);
NC1_ram_block3a9_clock_enable_0 = KB1_PROGRAM_ADDR[12];
NC1_ram_block3a9_clock_enable_1 = PC2_ram_rom_addr_reg[12];
NC1_ram_block3a9_PORT_A_data_out = MEMORY(NC1_ram_block3a9_PORT_A_data_in_reg, NC1_ram_block3a9_PORT_B_data_in_reg, NC1_ram_block3a9_PORT_A_address_reg, NC1_ram_block3a9_PORT_B_address_reg, NC1_ram_block3a9_PORT_A_write_enable_reg, NC1_ram_block3a9_PORT_B_write_enable_reg, , , NC1_ram_block3a9_clock_0, NC1_ram_block3a9_clock_1, NC1_ram_block3a9_clock_enable_0, NC1_ram_block3a9_clock_enable_1, , );
NC1_ram_block3a9 = NC1_ram_block3a9_PORT_A_data_out[0];
--NC1M325 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|ram_block3a9~PORTBDATAOUT0 at M4K_X11_Y7
NC1M325_PORT_A_data_in = VCC;
NC1M325_PORT_A_data_in_reg = DFFE(NC1M325_PORT_A_data_in, NC1M325_clock_0, , , NC1M325_clock_enable_0);
NC1M325_PORT_B_data_in = PC2_ram_rom_data_reg[1];
NC1M325_PORT_B_data_in_reg = DFFE(NC1M325_PORT_B_data_in, NC1M325_clock_1, , , NC1M325_clock_enable_1);
NC1M325_PORT_A_address = BUS(KB1_PROGRAM_ADDR[0], KB1_PROGRAM_ADDR[1], KB1_PROGRAM_ADDR[2], KB1_PROGRAM_ADDR[3], KB1_PROGRAM_ADDR[4], KB1_PROGRAM_ADDR[5], KB1_PROGRAM_ADDR[6], KB1_PROGRAM_ADDR[7], KB1_PROGRAM_ADDR[8], KB1_PROGRAM_ADDR[9], KB1_PROGRAM_ADDR[10], KB1_PROGRAM_ADDR[11]);
NC1M325_PORT_A_address_reg = DFFE(NC1M325_PORT_A_address, NC1M325_clock_0, , , NC1M325_clock_enable_0);
NC1M325_PORT_B_address = BUS(PC2_ram_rom_addr_reg[0], PC2_ram_rom_addr_reg[1], PC2_ram_rom_addr_reg[2], PC2_ram_rom_addr_reg[3], PC2_ram_rom_addr_reg[4], PC2_ram_rom_addr_reg[5], PC2_ram_rom_addr_reg[6], PC2_ram_rom_addr_reg[7], PC2_ram_rom_addr_reg[8], PC2_ram_rom_addr_reg[9], PC2_ram_rom_addr_reg[10], PC2_ram_rom_addr_reg[11]);
NC1M325_PORT_B_address_reg = DFFE(NC1M325_PORT_B_address, NC1M325_clock_1, , , NC1M325_clock_enable_1);
NC1M325_PORT_A_write_enable = GND;
NC1M325_PORT_A_write_enable_reg = DFFE(NC1M325_PORT_A_write_enable, NC1M325_clock_0, , , NC1M325_clock_enable_0);
NC1M325_PORT_B_write_enable = QC2L2;
NC1M325_PORT_B_write_enable_reg = DFFE(NC1M325_PORT_B_write_enable, NC1M325_clock_1, , , NC1M325_clock_enable_1);
NC1M325_clock_0 = GLOBAL(G1L1);
NC1M325_clock_1 = GLOBAL(A1L6);
NC1M325_clock_enable_0 = KB1_PROGRAM_ADDR[12];
NC1M325_clock_enable_1 = PC2_ram_rom_addr_reg[12];
NC1M325_PORT_B_data_out = MEMORY(NC1M325_PORT_A_data_in_reg, NC1M325_PORT_B_data_in_reg, NC1M325_PORT_A_address_reg, NC1M325_PORT_B_address_reg, NC1M325_PORT_A_write_enable_reg, NC1M325_PORT_B_write_enable_reg, , , NC1M325_clock_0, NC1M325_clock_1, NC1M325_clock_enable_0, NC1M325_clock_enable_1, , );
NC1M325 = NC1M325_PORT_B_data_out[0];
--NC1_ram_block3a1 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|ram_block3a1 at M4K_X11_Y6
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 8, Port B Logical Depth: 8192, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NC1_ram_block3a1_PORT_A_data_in = VCC;
NC1_ram_block3a1_PORT_A_data_in_reg = DFFE(NC1_ram_block3a1_PORT_A_data_in, NC1_ram_block3a1_clock_0, , , NC1_ram_block3a1_clock_enable_0);
NC1_ram_block3a1_PORT_B_data_in = PC2_ram_rom_data_reg[1];
NC1_ram_block3a1_PORT_B_data_in_reg = DFFE(NC1_ram_block3a1_PORT_B_data_in, NC1_ram_block3a1_clock_1, , , NC1_ram_block3a1_clock_enable_1);
NC1_ram_block3a1_PORT_A_address = BUS(KB1_PROGRAM_ADDR[0], KB1_PROGRAM_ADDR[1], KB1_PROGRAM_ADDR[2], KB1_PROGRAM_ADDR[3], KB1_PROGRAM_ADDR[4], KB1_PROGRAM_ADDR[5], KB1_PROGRAM_ADDR[6], KB1_PROGRAM_ADDR[7], KB1_PROGRAM_ADDR[8], KB1_PROGRAM_ADDR[9], KB1_PROGRAM_ADDR[10], KB1_PROGRAM_ADDR[11]);
NC1_ram_block3a1_PORT_A_address_reg = DFFE(NC1_ram_block3a1_PORT_A_address, NC1_ram_block3a1_clock_0, , , NC1_ram_block3a1_clock_enable_0);
NC1_ram_block3a1_PORT_B_address = BUS(PC2_ram_rom_addr_reg[0], PC2_ram_rom_addr_reg[1], PC2_ram_rom_addr_reg[2], PC2_ram_rom_addr_reg[3], PC2_ram_rom_addr_reg[4], PC2_ram_rom_addr_reg[5], PC2_ram_rom_addr_reg[6], PC2_ram_rom_addr_reg[7], PC2_ram_rom_addr_reg[8], PC2_ram_rom_addr_reg[9], PC2_ram_rom_addr_reg[10], PC2_ram_rom_addr_reg[11]);
NC1_ram_block3a1_PORT_B_address_reg = DFFE(NC1_ram_block3a1_PORT_B_address, NC1_ram_block3a1_clock_1, , , NC1_ram_block3a1_clock_enable_1);
NC1_ram_block3a1_PORT_A_write_enable = GND;
NC1_ram_block3a1_PORT_A_write_enable_reg = DFFE(NC1_ram_block3a1_PORT_A_write_enable, NC1_ram_block3a1_clock_0, , , NC1_ram_block3a1_clock_enable_0);
NC1_ram_block3a1_PORT_B_write_enable = QC2L1;
NC1_ram_block3a1_PORT_B_write_enable_reg = DFFE(NC1_ram_block3a1_PORT_B_write_enable, NC1_ram_block3a1_clock_1, , , NC1_ram_block3a1_clock_enable_1);
NC1_ram_block3a1_clock_0 = GLOBAL(G1L1);
NC1_ram_block3a1_clock_1 = GLOBAL(A1L6);
NC1_ram_block3a1_clock_enable_0 = !KB1_PROGRAM_ADDR[12];
NC1_ram_block3a1_clock_enable_1 = !PC2_ram_rom_addr_reg[12];
NC1_ram_block3a1_PORT_A_data_out = MEMORY(NC1_ram_block3a1_PORT_A_data_in_reg, NC1_ram_block3a1_PORT_B_data_in_reg, NC1_ram_block3a1_PORT_A_address_reg, NC1_ram_block3a1_PORT_B_address_reg, NC1_ram_block3a1_PORT_A_write_enable_reg, NC1_ram_block3a1_PORT_B_write_enable_reg, , , NC1_ram_block3a1_clock_0, NC1_ram_block3a1_clock_1, NC1_ram_block3a1_clock_enable_0, NC1_ram_block3a1_clock_enable_1, , );
NC1_ram_block3a1 = NC1_ram_block3a1_PORT_A_data_out[0];
--NC1M69 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|ram_block3a1~PORTBDATAOUT0 at M4K_X11_Y6
NC1M69_PORT_A_data_in = VCC;
NC1M69_PORT_A_data_in_reg = DFFE(NC1M69_PORT_A_data_in, NC1M69_clock_0, , , NC1M69_clock_enable_0);
NC1M69_PORT_B_data_in = PC2_ram_rom_data_reg[1];
NC1M69_PORT_B_data_in_reg = DFFE(NC1M69_PORT_B_data_in, NC1M69_clock_1, , , NC1M69_clock_enable_1);
NC1M69_PORT_A_address = BUS(KB1_PROGRAM_ADDR[0], KB1_PROGRAM_ADDR[1], KB1_PROGRAM_ADDR[2], KB1_PROGRAM_ADDR[3], KB1_PROGRAM_ADDR[4], KB1_PROGRAM_ADDR[5], KB1_PROGRAM_ADDR[6], KB1_PROGRAM_ADDR[7], KB1_PROGRAM_ADDR[8], KB1_PROGRAM_ADDR[9], KB1_PROGRAM_ADDR[10], KB1_PROGRAM_ADDR[11]);
NC1M69_PORT_A_address_reg = DFFE(NC1M69_PORT_A_address, NC1M69_clock_0, , , NC1M69_clock_enable_0);
NC1M69_PORT_B_address = BUS(PC2_ram_rom_addr_reg[0], PC2_ram_rom_addr_reg[1], PC2_ram_rom_addr_reg[2], PC2_ram_rom_addr_reg[3], PC2_ram_rom_addr_reg[4], PC2_ram_rom_addr_reg[5], PC2_ram_rom_addr_reg[6], PC2_ram_rom_addr_reg[7], PC2_ram_rom_addr_reg[8], PC2_ram_rom_addr_reg[9], PC2_ram_rom_addr_reg[10], PC2_ram_rom_addr_reg[11]);
NC1M69_PORT_B_address_reg = DFFE(NC1M69_PORT_B_address, NC1M69_clock_1, , , NC1M69_clock_enable_1);
NC1M69_PORT_A_write_enable = GND;
NC1M69_PORT_A_write_enable_reg = DFFE(NC1M69_PORT_A_write_enable, NC1M69_clock_0, , , NC1M69_clock_enable_0);
NC1M69_PORT_B_write_enable = QC2L1;
NC1M69_PORT_B_write_enable_reg = DFFE(NC1M69_PORT_B_write_enable, NC1M69_clock_1, , , NC1M69_clock_enable_1);
NC1M69_clock_0 = GLOBAL(G1L1);
NC1M69_clock_1 = GLOBAL(A1L6);
NC1M69_clock_enable_0 = !KB1_PROGRAM_ADDR[12];
NC1M69_clock_enable_1 = !PC2_ram_rom_addr_reg[12];
NC1M69_PORT_B_data_out = MEMORY(NC1M69_PORT_A_data_in_reg, NC1M69_PORT_B_data_in_reg, NC1M69_PORT_A_address_reg, NC1M69_PORT_B_address_reg, NC1M69_PORT_A_write_enable_reg, NC1M69_PORT_B_write_enable_reg, , , NC1M69_clock_0, NC1M69_clock_1, NC1M69_clock_enable_0, NC1M69_clock_enable_1, , );
NC1M69 = NC1M69_PORT_B_data_out[0];
--RC1L2 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|mux_hib:mux6|result_node[1]~97 at LCCOMB_X13_Y6_N30
RC1L2 = NC1_address_reg_a[0] & (NC1_ram_block3a9) # !NC1_address_reg_a[0] & NC1_ram_block3a1;
--K1L77 is CPU8051C1:inst|MCU80512:inst3|IROMD[1]~862 at LCCOMB_X15_Y10_N28
K1L77 = RC1L2 & !K1L179 & Z1L1;
--QB1L21 is CPU8051C1:inst|MCU80512:inst3|m3s025bo:U14|OPC[1]~ICOMBOUT at LCCOMB_X18_Y10⌨️ 快捷键说明
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