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--NC1_ram_block3a0 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|ram_block3a0
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 8, Port B Logical Depth: 8192, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NC1_ram_block3a0_PORT_A_data_in = VCC;
NC1_ram_block3a0_PORT_A_data_in_reg = DFFE(NC1_ram_block3a0_PORT_A_data_in, NC1_ram_block3a0_clock_0, , , NC1_ram_block3a0_clock_enable_0);
NC1_ram_block3a0_PORT_B_data_in = PC2_ram_rom_data_reg[0];
NC1_ram_block3a0_PORT_B_data_in_reg = DFFE(NC1_ram_block3a0_PORT_B_data_in, NC1_ram_block3a0_clock_1, , , NC1_ram_block3a0_clock_enable_1);
NC1_ram_block3a0_PORT_A_address = BUS(KB1_PROGRAM_ADDR[0], KB1_PROGRAM_ADDR[1], KB1_PROGRAM_ADDR[2], KB1_PROGRAM_ADDR[3], KB1_PROGRAM_ADDR[4], KB1_PROGRAM_ADDR[5], KB1_PROGRAM_ADDR[6], KB1_PROGRAM_ADDR[7], KB1_PROGRAM_ADDR[8], KB1_PROGRAM_ADDR[9], KB1_PROGRAM_ADDR[10], KB1_PROGRAM_ADDR[11]);
NC1_ram_block3a0_PORT_A_address_reg = DFFE(NC1_ram_block3a0_PORT_A_address, NC1_ram_block3a0_clock_0, , , NC1_ram_block3a0_clock_enable_0);
NC1_ram_block3a0_PORT_B_address = BUS(PC2_ram_rom_addr_reg[0], PC2_ram_rom_addr_reg[1], PC2_ram_rom_addr_reg[2], PC2_ram_rom_addr_reg[3], PC2_ram_rom_addr_reg[4], PC2_ram_rom_addr_reg[5], PC2_ram_rom_addr_reg[6], PC2_ram_rom_addr_reg[7], PC2_ram_rom_addr_reg[8], PC2_ram_rom_addr_reg[9], PC2_ram_rom_addr_reg[10], PC2_ram_rom_addr_reg[11]);
NC1_ram_block3a0_PORT_B_address_reg = DFFE(NC1_ram_block3a0_PORT_B_address, NC1_ram_block3a0_clock_1, , , NC1_ram_block3a0_clock_enable_1);
NC1_ram_block3a0_PORT_A_write_enable = GND;
NC1_ram_block3a0_PORT_A_write_enable_reg = DFFE(NC1_ram_block3a0_PORT_A_write_enable, NC1_ram_block3a0_clock_0, , , NC1_ram_block3a0_clock_enable_0);
NC1_ram_block3a0_PORT_B_write_enable = QC2L1;
NC1_ram_block3a0_PORT_B_write_enable_reg = DFFE(NC1_ram_block3a0_PORT_B_write_enable, NC1_ram_block3a0_clock_1, , , NC1_ram_block3a0_clock_enable_1);
NC1_ram_block3a0_clock_0 = VC1__clk1;
NC1_ram_block3a0_clock_1 = A1L5;
NC1_ram_block3a0_clock_enable_0 = !KB1_PROGRAM_ADDR[12];
NC1_ram_block3a0_clock_enable_1 = !PC2_ram_rom_addr_reg[12];
NC1_ram_block3a0_PORT_A_data_out = MEMORY(NC1_ram_block3a0_PORT_A_data_in_reg, NC1_ram_block3a0_PORT_B_data_in_reg, NC1_ram_block3a0_PORT_A_address_reg, NC1_ram_block3a0_PORT_B_address_reg, NC1_ram_block3a0_PORT_A_write_enable_reg, NC1_ram_block3a0_PORT_B_write_enable_reg, , , NC1_ram_block3a0_clock_0, NC1_ram_block3a0_clock_1, NC1_ram_block3a0_clock_enable_0, NC1_ram_block3a0_clock_enable_1, , );
NC1_ram_block3a0 = NC1_ram_block3a0_PORT_A_data_out[0];
--NC1M37 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|ram_block3a0~PORTBDATAOUT0
NC1M37_PORT_A_data_in = VCC;
NC1M37_PORT_A_data_in_reg = DFFE(NC1M37_PORT_A_data_in, NC1M37_clock_0, , , NC1M37_clock_enable_0);
NC1M37_PORT_B_data_in = PC2_ram_rom_data_reg[0];
NC1M37_PORT_B_data_in_reg = DFFE(NC1M37_PORT_B_data_in, NC1M37_clock_1, , , NC1M37_clock_enable_1);
NC1M37_PORT_A_address = BUS(KB1_PROGRAM_ADDR[0], KB1_PROGRAM_ADDR[1], KB1_PROGRAM_ADDR[2], KB1_PROGRAM_ADDR[3], KB1_PROGRAM_ADDR[4], KB1_PROGRAM_ADDR[5], KB1_PROGRAM_ADDR[6], KB1_PROGRAM_ADDR[7], KB1_PROGRAM_ADDR[8], KB1_PROGRAM_ADDR[9], KB1_PROGRAM_ADDR[10], KB1_PROGRAM_ADDR[11]);
NC1M37_PORT_A_address_reg = DFFE(NC1M37_PORT_A_address, NC1M37_clock_0, , , NC1M37_clock_enable_0);
NC1M37_PORT_B_address = BUS(PC2_ram_rom_addr_reg[0], PC2_ram_rom_addr_reg[1], PC2_ram_rom_addr_reg[2], PC2_ram_rom_addr_reg[3], PC2_ram_rom_addr_reg[4], PC2_ram_rom_addr_reg[5], PC2_ram_rom_addr_reg[6], PC2_ram_rom_addr_reg[7], PC2_ram_rom_addr_reg[8], PC2_ram_rom_addr_reg[9], PC2_ram_rom_addr_reg[10], PC2_ram_rom_addr_reg[11]);
NC1M37_PORT_B_address_reg = DFFE(NC1M37_PORT_B_address, NC1M37_clock_1, , , NC1M37_clock_enable_1);
NC1M37_PORT_A_write_enable = GND;
NC1M37_PORT_A_write_enable_reg = DFFE(NC1M37_PORT_A_write_enable, NC1M37_clock_0, , , NC1M37_clock_enable_0);
NC1M37_PORT_B_write_enable = QC2L1;
NC1M37_PORT_B_write_enable_reg = DFFE(NC1M37_PORT_B_write_enable, NC1M37_clock_1, , , NC1M37_clock_enable_1);
NC1M37_clock_0 = VC1__clk1;
NC1M37_clock_1 = A1L5;
NC1M37_clock_enable_0 = !KB1_PROGRAM_ADDR[12];
NC1M37_clock_enable_1 = !PC2_ram_rom_addr_reg[12];
NC1M37_PORT_B_data_out = MEMORY(NC1M37_PORT_A_data_in_reg, NC1M37_PORT_B_data_in_reg, NC1M37_PORT_A_address_reg, NC1M37_PORT_B_address_reg, NC1M37_PORT_A_write_enable_reg, NC1M37_PORT_B_write_enable_reg, , , NC1M37_clock_0, NC1M37_clock_1, NC1M37_clock_enable_0, NC1M37_clock_enable_1, , );
NC1M37 = NC1M37_PORT_B_data_out[0];
--NC1_address_reg_a[0] is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|address_reg_a[0]
NC1_address_reg_a[0] = DFFEAS(KB1_PROGRAM_ADDR[12], VC1__clk1, , , , , , , );
--RC1L1 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|mux_hib:mux6|result_node[0]~96
RC1L1 = NC1_address_reg_a[0] & NC1_ram_block3a8 # !NC1_address_reg_a[0] & (NC1_ram_block3a0);
--BB1_safe_q[5] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter6:inst17|lpm_counter:lpm_counter_component|cntr_dtd:auto_generated|safe_q[5]
BB1_safe_q[5] = DFFEAS(BB1L23, J2L23, , , , , , J2L22, );
--BB1_safe_q[2] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter6:inst17|lpm_counter:lpm_counter_component|cntr_dtd:auto_generated|safe_q[2]
BB1_safe_q[2] = DFFEAS(BB1L11, J2L23, , , , , , J2L22, );
--BB1_safe_q[3] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter6:inst17|lpm_counter:lpm_counter_component|cntr_dtd:auto_generated|safe_q[3]
BB1_safe_q[3] = DFFEAS(BB1L15, J2L23, , , , , , J2L22, );
--BB1_safe_q[4] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter6:inst17|lpm_counter:lpm_counter_component|cntr_dtd:auto_generated|safe_q[4]
BB1_safe_q[4] = DFFEAS(BB1L19, J2L23, , , , , , J2L22, );
--Z1L1 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|cmp_6:inst3|lpm_compare:lpm_compare_component|cmpr_s4h:auto_generated|aleb~21
Z1L1 = BB1_safe_q[5] # BB1_safe_q[4] & (BB1_safe_q[2] # BB1_safe_q[3]);
--MB1_L_EXPMEM is CPU8051C1:inst|MCU80512:inst3|m3s018bo:U10|L_EXPMEM
MB1_L_EXPMEM = DFFEAS(VCC, VC1__clk1, RST, , CB1_LDV2CK2, KB1_EXT_PROG_EN, , , VCC);
--K1L180 is CPU8051C1:inst|MCU80512:inst3|muxiromd~45
K1L180 = CB1_STATD[3] & K1L98 & (EB1L4 # !UB1L46);
--K1L179 is CPU8051C1:inst|MCU80512:inst3|muxiromd~1
K1L179 = MB1_L_EXPMEM # K1L180;
--K1L74 is CPU8051C1:inst|MCU80512:inst3|IROMD[0]~863
K1L74 = K1L179 & (S90) # !K1L179 & RC1L1 & (Z1L1);
--QB1L16 is CPU8051C1:inst|MCU80512:inst3|m3s025bo:U14|OPC[0]~ICOMBOUT
QB1L16 = !NB1_L_INTA & K1L74;
--QB1_L_OPLOAD is CPU8051C1:inst|MCU80512:inst3|m3s025bo:U14|L_OPLOAD
QB1_L_OPLOAD = DFFEAS(QB1L7, VC1__clk1, , , , , , , );
--QB1L53 is CPU8051C1:inst|MCU80512:inst3|m3s025bo:U14|dat_lat~23
QB1L53 = CB1_LDV2CK2 & CB1_STATD[1] & QB1_L_OPLOAD;
--NC1_ram_block3a9 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|ram_block3a9
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 8, Port B Logical Depth: 8192, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NC1_ram_block3a9_PORT_A_data_in = VCC;
NC1_ram_block3a9_PORT_A_data_in_reg = DFFE(NC1_ram_block3a9_PORT_A_data_in, NC1_ram_block3a9_clock_0, , , NC1_ram_block3a9_clock_enable_0);
NC1_ram_block3a9_PORT_B_data_in = PC2_ram_rom_data_reg[1];
NC1_ram_block3a9_PORT_B_data_in_reg = DFFE(NC1_ram_block3a9_PORT_B_data_in, NC1_ram_block3a9_clock_1, , , NC1_ram_block3a9_clock_enable_1);
NC1_ram_block3a9_PORT_A_address = BUS(KB1_PROGRAM_ADDR[0], KB1_PROGRAM_ADDR[1], KB1_PROGRAM_ADDR[2], KB1_PROGRAM_ADDR[3], KB1_PROGRAM_ADDR[4], KB1_PROGRAM_ADDR[5], KB1_PROGRAM_ADDR[6], KB1_PROGRAM_ADDR[7], KB1_PROGRAM_ADDR[8], KB1_PROGRAM_ADDR[9], KB1_PROGRAM_ADDR[10], KB1_PROGRAM_ADDR[11]);
NC1_ram_block3a9_PORT_A_address_reg = DFFE(NC1_ram_block3a9_PORT_A_address, NC1_ram_block3a9_clock_0, , , NC1_ram_block3a9_clock_enable_0);
NC1_ram_block3a9_PORT_B_address = BUS(PC2_ram_rom_addr_reg[0], PC2_ram_rom_addr_reg[1], PC2_ram_rom_addr_reg[2], PC2_ram_rom_addr_reg[3], PC2_ram_rom_addr_reg[4], PC2_ram_rom_addr_reg[5], PC2_ram_rom_addr_reg[6], PC2_ram_rom_addr_reg[7], PC2_ram_rom_addr_reg[8], PC2_ram_rom_addr_reg[9], PC2_ram_rom_addr_reg[10], PC2_ram_rom_addr_reg[11]);
NC1_ram_block3a9_PORT_B_address_reg = DFFE(NC1_ram_block3a9_PORT_B_address, NC1_ram_block3a9_clock_1, , , NC1_ram_block3a9_clock_enable_1);
NC1_ram_block3a9_PORT_A_write_enable = GND;
NC1_ram_block3a9_PORT_A_write_enable_reg = DFFE(NC1_ram_block3a9_PORT_A_write_enable, NC1_ram_block3a9_clock_0, , , NC1_ram_block3a9_clock_enable_0);
NC1_ram_block3a9_PORT_B_write_enable = QC2L2;
NC1_ram_block3a9_PORT_B_write_enable_reg = DFFE(NC1_ram_block3a9_PORT_B_write_enable, NC1_ram_block3a9_clock_1, , , NC1_ram_block3a9_clock_enable_1);
NC1_ram_block3a9_clock_0 = VC1__clk1;
NC1_ram_block3a9_clock_1 = A1L5;
NC1_ram_block3a9_clock_enable_0 = KB1_PROGRAM_ADDR[12];
NC1_ram_block3a9_clock_enable_1 = PC2_ram_rom_addr_reg[12];
NC1_ram_block3a9_PORT_A_data_out = MEMORY(NC1_ram_block3a9_PORT_A_data_in_reg, NC1_ram_block3a9_PORT_B_data_in_reg, NC1_ram_block3a9_PORT_A_address_reg, NC1_ram_block3a9_PORT_B_address_reg, NC1_ram_block3a9_PORT_A_write_enable_reg, NC1_ram_block3a9_PORT_B_write_enable_reg, , , NC1_ram_block3a9_clock_0, NC1_ram_block3a9_clock_1, NC1_ram_block3a9_clock_enable_0, NC1_ram_block3a9_clock_enable_1, , );
NC1_ram_block3a9 = NC1_ram_block3a9_PORT_A_data_out[0];
--NC1M325 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|ram_block3a9~PORTBDATAOUT0
NC1M325_PORT_A_data_in = VCC;
NC1M325_PORT_A_data_in_reg = DFFE(NC1M325_PORT_A_data_in, NC1M325_clock_0, , , NC1M325_clock_enable_0);
NC1M325_PORT_B_data_in = PC2_ram_rom_data_reg[1];
NC1M325_PORT_B_data_in_reg = DFFE(NC1M325_PORT_B_data_in, NC1M325_clock_1, , , NC1M325_clock_enable_1);
NC1M325_PORT_A_address = BUS(KB1_PROGRAM_ADDR[0], KB1_PROGRAM_ADDR[1], KB1_PROGRAM_ADDR[2], KB1_PROGRAM_ADDR[3], KB1_PROGRAM_ADDR[4], KB1_PROGRAM_ADDR[5], KB1_PROGRAM_ADDR[6], KB1_PROGRAM_ADDR[7], KB1_PROGRAM_ADDR[8], KB1_PROGRAM_ADDR[9], KB1_PROGRAM_ADDR[10], KB1_PROGRAM_ADDR[11]);
NC1M325_PORT_A_address_reg = DFFE(NC1M325_PORT_A_address, NC1M325_clock_0, , , NC1M325_clock_enable_0);
NC1M325_PORT_B_address = BUS(PC2_ram_rom_addr_reg[0], PC2_ram_rom_addr_reg[1], PC2_ram_rom_addr_reg[2], PC2_ram_rom_addr_reg[3], PC2_ram_rom_addr_reg[4], PC2_ram_rom_addr_reg[5], PC2_ram_rom_addr_reg[6], PC2_ram_rom_addr_reg[7], PC2_ram_rom_addr_reg[8], PC2_ram_rom_addr_reg[9], PC2_ram_rom_addr_reg[10], PC2_ram_rom_addr_reg[11]);
NC1M325_PORT_B_address_reg = DFFE(NC1M325_PORT_B_address, NC1M325_clock_1, , , NC1M325_clock_enable_1);
NC1M325_PORT_A_write_enable = GND;
NC1M325_PORT_A_write_enable_reg = DFFE(NC1M325_PORT_A_write_enable, NC1M325_clock_0, , , NC1M325_clock_enable_0);
NC1M325_PORT_B_write_enable = QC2L2;
NC1M325_PORT_B_write_enable_reg = DFFE(NC1M325_PORT_B_write_enable, NC1M325_clock_1, , , NC1M325_clock_enable_1);
NC1M325_clock_0 = VC1__clk1;
NC1M325_clock_1 = A1L5;
NC1M325_clock_enable_0 = KB1_PROGRAM_ADDR[12];
NC1M325_clock_enable_1 = PC2_ram_rom_addr_reg[12];
NC1M325_PORT_B_data_out = MEMORY(NC1M325_PORT_A_data_in_reg, NC1M325_PORT_B_data_in_reg, NC1M325_PORT_A_address_reg, NC1M325_PORT_B_address_reg, NC1M325_PORT_A_write_enable_reg, NC1M325_PORT_B_write_enable_reg, , , NC1M325_clock_0, NC1M325_clock_1, NC1M325_clock_enable_0, NC1M325_clock_enable_1, , );
NC1M325 = NC1M325_PORT_B_data_out[0];
--NC1_ram_block3a1 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|ram_block3a1
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 8, Port B Logical Depth: 8192, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NC1_ram_block3a1_PORT_A_data_in = VCC;
NC1_ram_block3a1_PORT_A_data_in_reg = DFFE(NC1_ram_block3a1_PORT_A_data_in, NC1_ram_block3a1_clock_0, , , NC1_ram_block3a1_clock_enable_0);
NC1_ram_block3a1_PORT_B_data_in = PC2_ram_rom_data_reg[1];
NC1_ram_block3a1_PORT_B_data_in_reg = DFFE(NC1_ram_block3a1_PORT_B_data_in, NC1_ram_block3a1_clock_1, , , NC1_ram_block3a1_clock_enable_1);
NC1_ram_block3a1_PORT_A_address = BUS(KB1_PROGRAM_ADDR[0], KB1_PROGRAM_ADDR[1], KB1_PROGRAM_ADDR[2], KB1_PROGRAM_ADDR[3], KB1_PROGRAM_ADDR[4], KB1_PROGRAM_ADDR[5], KB1_PROGRAM_ADDR[6], KB1_PROGRAM_ADDR[7], KB1_PROGRAM_ADDR[8], KB1_PROGRAM_ADDR[9], KB1_PROGRAM_ADDR[10], KB1_PROGRAM_ADDR[11]);
NC1_ram_block3a1_PORT_A_address_reg = DFFE(NC1_ram_block3a1_PORT_A_address, NC1_ram_block3a1_clock_0, , , NC1_ram_block3a1_clock_enable_0);
NC1_ram_block3a1_PORT_B_address = BUS(PC2_ram_rom_addr_reg[0], PC2_ram_rom_addr_reg[1], PC2_ram_rom_addr_reg[2], PC2_ram_rom_addr_reg[3], PC2_ram_rom_addr_reg[4], PC2_ram_rom_addr_reg[5], PC2_ram_rom_addr_reg[6], PC2_ram_rom_addr_reg[7], PC2_ram_rom_addr_reg[8], PC2_ram_rom_addr_reg[9], PC2_ram_rom_addr_reg[10], PC2_ram_rom_addr_reg[11]);
NC1_ram_block3a1_PORT_B_address_reg = DFFE(NC1_ram_block3a1_PORT_B_address, NC1_ram_block3a1_clock_1, , , NC1_ram_block3a1_clock_enable_1);
NC1_ram_block3a1_PORT_A_write_enable = GND;
NC1_ram_block3a1_PORT_A_write_enable_reg = DFFE(NC1_ram_block3a1_PORT_A_write_enable, NC1_ram_block3a1_clock_0, , , NC1_ram_block3a1_clock_enable_0);
NC1_ram_block3a1_PORT_B_write_enable = QC2L1;
NC1_ram_block3a1_PORT_B_write_enable_reg = DFFE(NC1_ram_block3a1_PORT_B_write_enable, NC1_ram_block3a1_clock_1, , , NC1_ram_block3a1_clock_enable_1);
NC1_ram_block3a1_clock_0 = VC1__clk1;
NC1_ram_block3a1_clock_1 = A1L5;
NC1_ram_block3a1_clock_enable_0 = !KB1_PROGRAM_ADDR[12];
NC1_ram_block3a1_clock_enable_1 = !PC2_ram_rom_addr_reg[12];
NC1_ram_block3a1_PORT_A_data_out = MEMORY(NC1_ram_block3a1_PORT_A_data_in_reg, NC1_ram_block3a1_PORT_B_data_in_reg, NC1_ram_block3a1_PORT_A_address_reg, NC1_ram_block3a1_PORT_B_address_reg, NC1_ram_block3a1_PORT_A_write_enable_reg, NC1_ram_block3a1_PORT_B_write_enable_reg, , , NC1_ram_block3a1_clock_0, NC1_ram_block3a1_clock_1, NC1_ram_block3a1_clock_enable_0, NC1_ram_block3a1_clock_enable_1, , );
NC1_ram_block3a1 = NC1_ram_block3a1_PORT_A_data_out[0];
--NC1M69 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|ram_block3a1~PORTBDATAOUT0
NC1M69_PORT_A_data_in = VCC;
NC1M69_PORT_A_data_in_reg = DFFE(NC1M69_PORT_A_data_in, NC1M69_clock_0, , , NC1M69_clock_enable_0);
NC1M69_PORT_B_data_in = PC2_ram_rom_data_reg[1];
NC1M69_PORT_B_data_in_reg = DFFE(NC1M69_PORT_B_data_in, NC1M69_clock_1, , , NC1M69_clock_enable_1);
NC1M69_PORT_A_address = BUS(KB1_PROGRAM_ADDR[0], KB1_PROGRAM_ADDR[1], KB1_PROGRAM_ADDR[2], KB1_PROGRAM_ADDR[3], KB1_PROGRAM_ADDR[4], KB1_PROGRAM_ADDR[5], KB1_PROGRAM_ADDR[6], KB1_PROGRAM_ADDR[7], KB1_PROGRAM_ADDR[8], KB1_PROGRAM_ADDR[9], KB1_PROGRAM_ADDR[10], KB1_PROGRAM_ADDR[11]);
NC1M69_PORT_A_address_reg = DFFE(NC1M69_PORT_A_address, NC1M69_clock_0, , , NC1M69_clock_enable_0);
NC1M69_PORT_B_address = BUS(PC2_ram_rom_addr_reg[0], PC2_ram_rom_addr_reg[1], PC2_ram_rom_addr_reg[2], PC2_ram_rom_addr_reg[3], PC2_ram_rom_addr_reg[4], PC2_ram_rom_addr_reg[5], PC2_ram_rom_addr_reg[6], PC2_ram_rom_addr_reg[7], PC2_ram_rom_addr_reg[8], PC2_ram_rom_addr_reg[9], PC2_ram_rom_addr_reg[10], PC2_ram_rom_addr_reg[11]);
NC1M69_PORT_B_address_reg = DFFE(NC1M69_PORT_B_address, NC1M69_clock_1, , , NC1M69_clock_enable_1);
NC1M69_PORT_A_write_enable = GND;
NC1M69_PORT_A_write_enable_reg = DFFE(NC1M69_PORT_A_write_enable, NC1M69_clock_0, , , NC1M69_clock_enable_0);
NC1M69_PORT_B_write_enable = QC2L1;
NC1M69_PORT_B_write_enable_reg = DFFE(NC1M69_PORT_B_write_enable, NC1M69_clock_1, , , NC1M69_clock_enable_1);
NC1M69_clock_0 = VC1__clk1;
NC1M69_clock_1 = A1L5;
NC1M69_clock_enable_0 = !KB1_PROGRAM_ADDR[12];
NC1M69_clock_enable_1 = !PC2_ram_rom_addr_reg[12];
NC1M69_PORT_B_data_out = MEMORY(NC1M69_PORT_A_data_in_reg, NC1M69_PORT_B_data_in_reg, NC1M69_PORT_A_address_reg, NC1M69_PORT_B_address_reg, NC1M69_PORT_A_write_enable_reg, NC1M69_PORT_B_write_enable_reg, , , NC1M69_clock_0, NC1M69_clock_1, NC1M69_clock_enable_0, NC1M69_clock_enable_1, , );
NC1M69 = NC1M69_PORT_B_data_out[0];
--RC1L2 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|mux_hib:mux6|result_node[1]~97
RC1L2 = NC1_address_reg_a[0] & NC1_ram_block3a9 # !NC1_address_reg_a[0] & (NC1_ram_block3a1);
--K1L77 is CPU8051C1:inst|MCU80512:inst3|IROMD[1]~862
K1L77 = RC1L2 & Z1L1 & !K1L179;
--QB1L21 is CPU8051C1:inst|MCU80512:inst3|m3s025bo:U14|OPC[1]~ICOMBOUT
QB1L21 = NB1_L_INTA # K1L77;
--NC1_ram_block3a10 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|ram_block3a10
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 8, Port B Logical Depth: 8192, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NC1_ram_block3a10_PORT_A_data_in = VCC;
NC1_ram_block3a10_PORT_A_data_in_reg = DFFE(NC1_ram_block3a10_PORT_A_data_in, NC1_ram_block3a10_clock_0, , , NC1_ram_block3a10_clock_enable_0);
NC1_ram_block3a10_PORT_B_data_in = PC2_ram_rom_data_reg[2];
NC1_ram_block3a10_PORT_B_data_in_reg = DFFE(NC1_ram_block3a10_PORT_B_data_in, NC1_ram_block3a10_clock_1, , , NC1_ram_block3a10_clock_enable_1);
NC1_ram_block3a10_PORT_A_address = BUS(KB1_PROGRAM_ADDR[0], KB1_PROGRAM_ADDR[1], KB1_PROGRAM_ADDR[2], KB1_PROGRAM_ADDR[3], KB1_PROGRAM_ADDR[4], KB1_PROGRAM_ADDR[5], KB1_PROGRAM_ADDR[6], KB1_PROGRAM_ADDR[7], KB1_PROGRAM_ADDR[8], KB1_PROGRAM_ADDR[9], KB1_PROGRAM_ADDR[10], KB1_PROGRAM_ADDR[11]);
NC1_ram_block3a10_PORT_A_address_reg = DFFE(NC1_ram_block3a10_PORT_A_address, NC1_ram_block3a10_clock_0, , , NC1_ram_block3a10_clock_enable_0);
NC1_ram_block3a10_PORT_B_address = BUS(PC2_ram_rom_addr_reg[0], PC2_ram_rom_addr_reg[1], PC2_ram_rom_addr_reg[2], PC2_ram_rom_addr_reg[3], PC2_ram_rom_addr_reg[4], PC2_ram_rom_addr_reg[5], PC2_ram_rom_addr_reg[6], PC2_ram_rom_addr_reg[7], PC2_ram_rom_addr_reg[8], PC2_ram_rom_addr_reg[9], PC2_ram_rom_addr_reg[10], PC2_ram_rom_addr_reg[11]);
NC1_ram_block3a10_PORT_B_address_reg = DFFE(NC1_ram_block3a10_PORT_B_address, NC1_ram_block3a10_clock_1, , , NC1_ram_block3a10_clock_enable_1);
NC1_ram_block3a10_PORT_A_write_enable = GND;
NC1_ram_block3a10_PORT_A_write_enable_reg = DFFE(NC1_ram_block3a10_PORT_A_write_enable, NC1_ram_block3a10_clock_0, , , NC1_ram_block3a10_clock_enable_0);
NC1_ram_block3a10_PORT_B_write_enable = QC2L2;
NC1_ram_block3a10_PORT_B_write_enable_reg = DFFE(NC1_ram_block3a10_PORT_B_write_enable, NC1_ram_block3a10_clock_1, , , NC1_ram_block3a10_clock_enable_1);
NC1_ram_block3a10_clock_0 = VC1__clk1;
NC1_ram_block3a10_clock_1 = A1L5;
NC1_ram_block3a10_clock_enable_0 = KB1_PROGRAM_ADDR[12];
NC1_ram_block3a10_clock_enable_1 = PC2_ram_rom_addr_reg[12];
NC1_ram_block3a10_PORT_A_data_out = MEMORY(NC1_ram_block3a10_PORT_A_data_in_reg, NC1_ram_block3a10_PORT_B_data_in_reg, NC1_ram_block3a10_PORT_A_address_reg, NC1_ram_block3a10_PORT_B_address_reg, NC1_ram_block3a10_PORT_A_write_enable_reg, NC1_ram_block3a10_PORT_B_write_enable_reg, , , NC1_ram_block3a10_clock_0, NC1_ram_block3a10_clock_1, NC1_ram_block3a10_clock_enable_0, NC1_ram_block3a10_clock_enable_1, , );
NC1_ram_block3a10 = NC1_ram_block3a10_PORT_A_data_out[0];
--NC1M357 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|ram_block3a10~PORTBDATAOUT0
NC1M357_PORT_A_data_in = VCC;
NC1M357_PORT_A_data_in_reg = DFFE(NC1M357_PORT_A_data_in, NC1M357_clock_0, , , NC1M357_clock_enable_0);
NC1M357_PORT_B_data_in = PC2_ram_rom_data_reg[2];
NC1M357_PORT_B_data_in_reg = DFFE(NC1M357_PORT_B_data_in, NC1M357_clock_1, , , NC1M357_clock_enable_1);
NC1M357_PORT_A_address = BUS(KB1_PROGRAM_ADDR[0], KB1_PROGRAM_ADDR[1], KB1_PROGRAM_ADDR[2], KB1_PROGRAM_ADDR[3], KB1_PROGRAM_ADDR[4], KB1_PROGRAM_ADDR[5], KB1_PROGRAM_ADDR[6], KB1_PROGRAM_ADDR[7], KB1_PROGRAM_ADDR[8], KB1_PROGRAM_ADDR[9], KB1_PROGRAM_ADDR[10], KB1_PROGRAM_ADDR[11]);
NC1M357_PORT_A_address_reg = DFFE(NC1M357_PORT_A_address, NC1M357_clock_0, , , NC1M357_clock_enable_0);
NC1M357_PORT_B_address = BUS(PC2_ram_rom_addr_reg[0], PC2_ram_rom_addr_reg[1], PC2_ram_rom_addr_reg[2], PC2_ram_rom_addr_reg[3], PC2_ram_rom_addr_reg[4], PC2_ram_rom_addr_reg[5], PC2_ram_rom_addr_reg[6], PC2_ram_rom_addr_reg[7], PC2_ram_rom_addr_reg[8], PC2_ram_rom_addr_reg[9], PC2_ram_rom_addr_reg[10], PC2_ram_rom_addr_reg[11]);
NC1M357_PORT_B_address_reg = DFFE(NC1M357_PORT_B_address, NC1M357_clock_1, , , NC1M357_clock_enable_1);
NC1M357_PORT_A_write_enable = GND;
NC1M357_PORT_A_write_enable_reg = DFFE(NC1M357_PORT_A_write_enable, NC1M357_clock_0, , , NC1M357_clock_enable_0);
NC1M357_PORT_B_write_enable = QC2L2;
NC1M357_PORT_B_write_enable_reg = DFFE(NC1M357_PORT_B_write_enable, NC1M357_clock_1, , , NC1M357_clock_enable_1);
NC1M357_clock_0 = VC1__clk1;
NC1M357_clock_1 = A1L5;
NC1M357_clock_enable_0 = KB1_PROGRAM_ADDR[12];
NC1M357_clock_enable_1 = PC2_ram_rom_addr_reg[12];
NC1M357_PORT_B_data_out = MEMORY(NC1M357_PORT_A_data_in_reg, NC1M357_PORT_B_data_in_reg, NC1M357_PORT_A_address_reg, NC1M357_PORT_B_address_reg, NC1M357_PORT_A_write_enable_reg, NC1M357_PORT_B_write_enable_reg, , , NC1M357_clock_0, NC1M357_clock_1, NC1M357_clock_enable_0, NC1M357_clock_enable_1, , );
NC1M357 = NC1M357_PORT_B_data_out[0];
--NC1_ram_block3a2 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|ram_block3a2
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 8, Port B Logical Depth: 8192, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NC1_ram_block3a2_PORT_A_data_in = VCC;
NC1_ram_block3a2_PORT_A_data_in_reg = DFFE(NC1_ram_block3a2_PORT_A_data_in, NC1_ram_block3a2_clock_0, , , NC1_ram_block3a2_clock_enable_0);
NC1_ram_block3a2_PORT_B_data_in = PC2_ram_rom_data_reg[2];
NC1_ram_block3a2_PORT_B_data_in_reg = DFFE(NC1_ram_block3a2_PORT_B_data_in, NC1_ram_block3a2_clock_1, , , NC1_ram_block3a2_clock_enable_1);
NC1_ram_block3a2_PORT_A_address = BUS(KB1_PROGRAM_ADDR[0], KB1_PROGRAM_ADDR[1], KB1_PROGRAM_ADDR[2], KB1_PROGRAM_ADDR[3], KB1_PROGRAM_ADDR[4], KB1_PROGRAM_ADDR[5], KB1_PROGRAM_ADDR[6], KB1_PROGRAM_ADDR[7], KB1_PROGRAM_ADDR[8], KB1_PROGRAM_ADDR[9], KB1_PROGRAM_ADDR[10], KB1_PROGRAM_ADDR[11]);
NC1_ram_block3a2_PORT_A_address_reg = DFFE(NC1_ram_block3a2_PORT_A_address, NC1_ram_block3a2_clock_0, , , NC1_ram_block3a2_clock_enable_0);
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