mcu8951.map.eqn

此示例是8051核加频率计的联合设计,带有8051IP核资料

--JC1_DAT[1] is CPU8051C1:inst|MCU80512:inst3|m3s028bo:U15|m3s030bo:U9|DAT[1]
JC1_DAT[1] = DFFEAS(JC1L16, VC1__clk1,  ,  , JC1L7,  ,  , !K1_CLEAR,  );


--JC1L11 is CPU8051C1:inst|MCU80512:inst3|m3s028bo:U15|m3s030bo:U9|DAT[0]~ICOMBOUT
JC1L11 = RB1_NEWDATA & JB1_RAMDI[0] # !RB1_NEWDATA & (JC1_DAT[1]);


--BC1L4 is CPU8051C1:inst|MCU80512:inst3|m3s008bo:U7|m3s039bo:U2|A001~15
BC1L4 = !JB1_L_FA[1] & !JB1_L_FA[2] & JB1_L_FA[0];


--JC1L4 is CPU8051C1:inst|MCU80512:inst3|m3s028bo:U15|m3s030bo:U9|DAT[0]~110
JC1L4 = BC1L53 & !BC1L4 & (!RB1L323 # !RB1_DATAEN) # !BC1L53 & (!RB1L323 # !RB1_DATAEN);


--JC1L7 is CPU8051C1:inst|MCU80512:inst3|m3s028bo:U15|m3s030bo:U9|DAT[0]~111
JC1L7 = !K1_CLEAR # !JC1L4;


--RB1L26 is CPU8051C1:inst|MCU80512:inst3|m3s028bo:U15|DATAEN~175
RB1L26 = RB1L366 & !CB1_LDV2CK1 & (RB1_TSEND # !RB1L161);


--RB1L30 is CPU8051C1:inst|MCU80512:inst3|m3s028bo:U15|DATAEN~ICOMBOUT
RB1L30 = !RB1L373 & !RB1_Q6 & (RB1_DATAEN # RB1L26);


--MB1L324 is CPU8051C1:inst|MCU80512:inst3|m3s018bo:U10|PORT3_SFR[0]~ICOMBOUT
MB1L324 = !JB1_RAMDI[0];


--N1_inst is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|START:inst1|inst
N1_inst = DFFEAS(N1L9, N1_inst3, !RST,  ,  ,  ,  ,  ,  );


--X1_safe_q[9] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_9gd:auto_generated|safe_q[9]
X1_safe_q[9] = DFFEAS(X1L39, B1_inst19,  ,  ,  ,  ,  ,  ,  );


--V1L50 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_shiftreg32:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[9]~ICOMBOUT
V1L50 = N1_inst & (X1_safe_q[9]) # !N1_inst & V1_dffs[8];


--V1_dffs[5] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_shiftreg32:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[5]
V1_dffs[5] = DFFEAS(V1L30, J2L8,  ,  ,  ,  ,  ,  ,  );


--X1_safe_q[6] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_9gd:auto_generated|safe_q[6]
X1_safe_q[6] = DFFEAS(X1L27, B1_inst19,  ,  ,  ,  ,  ,  ,  );


--V1L35 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_shiftreg32:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[6]~ICOMBOUT
V1L35 = N1_inst & (X1_safe_q[6]) # !N1_inst & V1_dffs[5];


--V1_dffs[2] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_shiftreg32:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[2]
V1_dffs[2] = DFFEAS(V1L15, J2L8,  ,  ,  ,  ,  ,  ,  );


--X1_safe_q[3] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_9gd:auto_generated|safe_q[3]
X1_safe_q[3] = DFFEAS(X1L15, B1_inst19,  ,  ,  ,  ,  ,  ,  );


--V1L20 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_shiftreg32:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[3]~ICOMBOUT
V1L20 = N1_inst & (X1_safe_q[3]) # !N1_inst & V1_dffs[2];


--B1_inst9 is CPU8051C1:inst|inst9
B1_inst9 = DFFEAS(B1L19, VC1__clk1,  ,  ,  ,  ,  ,  ,  );


--B1L24 is CPU8051C1:inst|inst19~ICOMBOUT
B1L24 = !B1_inst19;


--AB1_safe_q[4] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter2:inst7|lpm_counter:lpm_counter_component|cntr_unf:auto_generated|safe_q[4]
AB1_safe_q[4] = DFFEAS(AB1L25, B1_inst19,  ,  ,  , ~GND,  , N1_inst, AB1_modulus_trigger);


--AB1_safe_q[1] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter2:inst7|lpm_counter:lpm_counter_component|cntr_unf:auto_generated|safe_q[1]
AB1_safe_q[1] = DFFEAS(AB1L13, B1_inst19,  ,  ,  , ~GND,  , N1_inst, AB1_modulus_trigger);


--AB1_safe_q[2] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter2:inst7|lpm_counter:lpm_counter_component|cntr_unf:auto_generated|safe_q[2]
AB1_safe_q[2] = DFFEAS(AB1L17, B1_inst19,  ,  ,  , ~GND,  , N1_inst, AB1_modulus_trigger);


--AB1_safe_q[3] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter2:inst7|lpm_counter:lpm_counter_component|cntr_unf:auto_generated|safe_q[3]
AB1_safe_q[3] = DFFEAS(AB1L21, B1_inst19,  ,  ,  , ~GND,  , N1_inst, AB1_modulus_trigger);


--AB1_safe_q[0] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter2:inst7|lpm_counter:lpm_counter_component|cntr_unf:auto_generated|safe_q[0]
AB1_safe_q[0] = DFFEAS(AB1L9, B1_inst19,  ,  ,  , ~GND,  , N1_inst, AB1_modulus_trigger);


--AB1L4 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter2:inst7|lpm_counter:lpm_counter_component|cntr_unf:auto_generated|cmpr1_aeb_int~35
AB1L4 = AB1_safe_q[1] & !AB1_safe_q[2] & AB1_safe_q[3] & AB1_safe_q[0];


--AB1_safe_q[5] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter2:inst7|lpm_counter:lpm_counter_component|cntr_unf:auto_generated|safe_q[5]
AB1_safe_q[5] = DFFEAS(AB1L29, B1_inst19,  ,  ,  , ~GND,  , N1_inst, AB1_modulus_trigger);


--AB1L1 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter2:inst7|lpm_counter:lpm_counter_component|cntr_unf:auto_generated|cmpr1_aeb_int~0
AB1L1 = !AB1_safe_q[4] & AB1L4 & AB1_safe_q[5];


--AB1L9 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter2:inst7|lpm_counter:lpm_counter_component|cntr_unf:auto_generated|counter_cella0~COMBOUT
AB1L9 = AB1_safe_q[0] $ VCC;

--AB1L10 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter2:inst7|lpm_counter:lpm_counter_component|cntr_unf:auto_generated|counter_cella0~COUT
AB1L10 = CARRY(AB1_safe_q[0]);


--AB1L13 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter2:inst7|lpm_counter:lpm_counter_component|cntr_unf:auto_generated|counter_cella1~COMBOUT
AB1L13 = AB1_safe_q[1] & !AB1L10 # !AB1_safe_q[1] & (AB1L10 # GND);

--AB1L14 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter2:inst7|lpm_counter:lpm_counter_component|cntr_unf:auto_generated|counter_cella1~COUT
AB1L14 = CARRY(!AB1L10 # !AB1_safe_q[1]);


--AB1L17 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter2:inst7|lpm_counter:lpm_counter_component|cntr_unf:auto_generated|counter_cella2~COMBOUT
AB1L17 = AB1_safe_q[2] & (AB1L14 $ GND) # !AB1_safe_q[2] & !AB1L14 & VCC;

--AB1L18 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter2:inst7|lpm_counter:lpm_counter_component|cntr_unf:auto_generated|counter_cella2~COUT
AB1L18 = CARRY(AB1_safe_q[2] & !AB1L14);


--AB1L21 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter2:inst7|lpm_counter:lpm_counter_component|cntr_unf:auto_generated|counter_cella3~COMBOUT
AB1L21 = AB1_safe_q[3] & !AB1L18 # !AB1_safe_q[3] & (AB1L18 # GND);

--AB1L22 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter2:inst7|lpm_counter:lpm_counter_component|cntr_unf:auto_generated|counter_cella3~COUT
AB1L22 = CARRY(!AB1L18 # !AB1_safe_q[3]);


--AB1L25 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter2:inst7|lpm_counter:lpm_counter_component|cntr_unf:auto_generated|counter_cella4~COMBOUT
AB1L25 = AB1_safe_q[4] & (AB1L22 $ GND) # !AB1_safe_q[4] & !AB1L22 & VCC;

--AB1L26 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter2:inst7|lpm_counter:lpm_counter_component|cntr_unf:auto_generated|counter_cella4~COUT
AB1L26 = CARRY(AB1_safe_q[4] & !AB1L22);


--AB1L29 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter2:inst7|lpm_counter:lpm_counter_component|cntr_unf:auto_generated|counter_cella5~COMBOUT
AB1L29 = AB1_safe_q[5] & !AB1L26 # !AB1_safe_q[5] & (AB1L26 # GND);

--AB1L30 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter2:inst7|lpm_counter:lpm_counter_component|cntr_unf:auto_generated|counter_cella5~COUT
AB1L30 = CARRY(!AB1L26 # !AB1_safe_q[5]);


--AB1_modulus_trigger is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|counter2:inst7|lpm_counter:lpm_counter_component|cntr_unf:auto_generated|modulus_trigger
AB1_modulus_trigger = AB1L1 # !AB1L30;


--X1_safe_q[1] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_9gd:auto_generated|safe_q[1]
X1_safe_q[1] = DFFEAS(X1L7, B1_inst19,  ,  ,  ,  ,  ,  ,  );


--V1_dffs[0] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_shiftreg32:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[0]
V1_dffs[0] = DFFEAS(V1L5, J2L8,  ,  ,  ,  ,  ,  ,  );


--V1L10 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_shiftreg32:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[1]~ICOMBOUT
V1L10 = N1_inst & X1_safe_q[1] # !N1_inst & (V1_dffs[0]);


--X1_safe_q[4] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_9gd:auto_generated|safe_q[4]
X1_safe_q[4] = DFFEAS(X1L19, B1_inst19,  ,  ,  ,  ,  ,  ,  );


--V1L25 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_shiftreg32:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[4]~ICOMBOUT
V1L25 = N1_inst & X1_safe_q[4] # !N1_inst & (V1_dffs[3]);


--X1_safe_q[8] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_9gd:auto_generated|safe_q[8]
X1_safe_q[8] = DFFEAS(X1L35, B1_inst19,  ,  ,  ,  ,  ,  ,  );


--V1_dffs[7] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_shiftreg32:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[7]
V1_dffs[7] = DFFEAS(V1L40, J2L8,  ,  ,  ,  ,  ,  ,  );


--V1L45 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_shiftreg32:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[8]~ICOMBOUT
V1L45 = N1_inst & X1_safe_q[8] # !N1_inst & (V1_dffs[7]);


--V1_dffs[22] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_shiftreg32:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[22]
V1_dffs[22] = DFFEAS(V1L115, J2L8,  ,  ,  ,  ,  ,  ,  );


--X1_safe_q[23] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_counter0:inst2|lpm_counter:lpm_counter_component|cntr_9gd:auto_generated|safe_q[23]
X1_safe_q[23] = DFFEAS(X1L95, B1_inst19,  ,  ,  ,  ,  ,  ,  );


--V1L120 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_shiftreg32:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[23]~ICOMBOUT
V1L120 = N1_inst & (X1_safe_q[23]) # !N1_inst & V1_dffs[22];


--H1_hub_tdo is sld_hub:sld_hub_inst|hub_tdo
H1_hub_tdo = AMPP_FUNCTION(!A1L5, H1L19, !ZC1_state[8]);


--CB1_S_EN is CPU8051C1:inst|MCU80512:inst3|m3s001bo:U1|S_EN
CB1_S_EN = DFFEAS(VCC, VC1__clk1, RST,  ,  , CB1_SME,  ,  , VCC);


--K1L4 is CPU8051C1:inst|MCU80512:inst3|CLEAR~ICOMBOUT
K1L4 = CB1_S_EN # K1_CLEAR;


--CB1_SMD is CPU8051C1:inst|MCU80512:inst3|m3s001bo:U1|SMD
CB1_SMD = DFFEAS(VCC, VC1__clk1, RST,  , !CB1_LDV2CK1, CB1_SMC,  ,  , VCC);


--CB1L59 is CPU8051C1:inst|MCU80512:inst3|m3s001bo:U1|STATD[1]~11
CB1L59 = !PB1_L_PCON[0] & !CB1_LDV2CK2;


--NB1_L_INTA is CPU8051C1:inst|MCU80512:inst3|m3s019bo:U11|L_INTA
NB1_L_INTA = DFFEAS(NB1L150, VC1__clk1, RST,  ,  ,  ,  , !K1_CLEAR,  );


--NC1_ram_block3a8 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|ram_block3a8
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 4096, Port A Width: 1, Port B Depth: 4096, Port B Width: 1
--Port A Logical Depth: 8192, Port A Logical Width: 8, Port B Logical Depth: 8192, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NC1_ram_block3a8_PORT_A_data_in = VCC;
NC1_ram_block3a8_PORT_A_data_in_reg = DFFE(NC1_ram_block3a8_PORT_A_data_in, NC1_ram_block3a8_clock_0, , , NC1_ram_block3a8_clock_enable_0);
NC1_ram_block3a8_PORT_B_data_in = PC2_ram_rom_data_reg[0];
NC1_ram_block3a8_PORT_B_data_in_reg = DFFE(NC1_ram_block3a8_PORT_B_data_in, NC1_ram_block3a8_clock_1, , , NC1_ram_block3a8_clock_enable_1);
NC1_ram_block3a8_PORT_A_address = BUS(KB1_PROGRAM_ADDR[0], KB1_PROGRAM_ADDR[1], KB1_PROGRAM_ADDR[2], KB1_PROGRAM_ADDR[3], KB1_PROGRAM_ADDR[4], KB1_PROGRAM_ADDR[5], KB1_PROGRAM_ADDR[6], KB1_PROGRAM_ADDR[7], KB1_PROGRAM_ADDR[8], KB1_PROGRAM_ADDR[9], KB1_PROGRAM_ADDR[10], KB1_PROGRAM_ADDR[11]);
NC1_ram_block3a8_PORT_A_address_reg = DFFE(NC1_ram_block3a8_PORT_A_address, NC1_ram_block3a8_clock_0, , , NC1_ram_block3a8_clock_enable_0);
NC1_ram_block3a8_PORT_B_address = BUS(PC2_ram_rom_addr_reg[0], PC2_ram_rom_addr_reg[1], PC2_ram_rom_addr_reg[2], PC2_ram_rom_addr_reg[3], PC2_ram_rom_addr_reg[4], PC2_ram_rom_addr_reg[5], PC2_ram_rom_addr_reg[6], PC2_ram_rom_addr_reg[7], PC2_ram_rom_addr_reg[8], PC2_ram_rom_addr_reg[9], PC2_ram_rom_addr_reg[10], PC2_ram_rom_addr_reg[11]);
NC1_ram_block3a8_PORT_B_address_reg = DFFE(NC1_ram_block3a8_PORT_B_address, NC1_ram_block3a8_clock_1, , , NC1_ram_block3a8_clock_enable_1);
NC1_ram_block3a8_PORT_A_write_enable = GND;
NC1_ram_block3a8_PORT_A_write_enable_reg = DFFE(NC1_ram_block3a8_PORT_A_write_enable, NC1_ram_block3a8_clock_0, , , NC1_ram_block3a8_clock_enable_0);
NC1_ram_block3a8_PORT_B_write_enable = QC2L2;
NC1_ram_block3a8_PORT_B_write_enable_reg = DFFE(NC1_ram_block3a8_PORT_B_write_enable, NC1_ram_block3a8_clock_1, , , NC1_ram_block3a8_clock_enable_1);
NC1_ram_block3a8_clock_0 = VC1__clk1;
NC1_ram_block3a8_clock_1 = A1L5;
NC1_ram_block3a8_clock_enable_0 = KB1_PROGRAM_ADDR[12];
NC1_ram_block3a8_clock_enable_1 = PC2_ram_rom_addr_reg[12];
NC1_ram_block3a8_PORT_A_data_out = MEMORY(NC1_ram_block3a8_PORT_A_data_in_reg, NC1_ram_block3a8_PORT_B_data_in_reg, NC1_ram_block3a8_PORT_A_address_reg, NC1_ram_block3a8_PORT_B_address_reg, NC1_ram_block3a8_PORT_A_write_enable_reg, NC1_ram_block3a8_PORT_B_write_enable_reg, , , NC1_ram_block3a8_clock_0, NC1_ram_block3a8_clock_1, NC1_ram_block3a8_clock_enable_0, NC1_ram_block3a8_clock_enable_1, , );
NC1_ram_block3a8 = NC1_ram_block3a8_PORT_A_data_out[0];

--NC1M293 is rom4kb:inst5|altsyncram:altsyncram_component|altsyncram_i361:auto_generated|altsyncram_00a2:altsyncram1|ram_block3a8~PORTBDATAOUT0
NC1M293_PORT_A_data_in = VCC;
NC1M293_PORT_A_data_in_reg = DFFE(NC1M293_PORT_A_data_in, NC1M293_clock_0, , , NC1M293_clock_enable_0);
NC1M293_PORT_B_data_in = PC2_ram_rom_data_reg[0];
NC1M293_PORT_B_data_in_reg = DFFE(NC1M293_PORT_B_data_in, NC1M293_clock_1, , , NC1M293_clock_enable_1);
NC1M293_PORT_A_address = BUS(KB1_PROGRAM_ADDR[0], KB1_PROGRAM_ADDR[1], KB1_PROGRAM_ADDR[2], KB1_PROGRAM_ADDR[3], KB1_PROGRAM_ADDR[4], KB1_PROGRAM_ADDR[5], KB1_PROGRAM_ADDR[6], KB1_PROGRAM_ADDR[7], KB1_PROGRAM_ADDR[8], KB1_PROGRAM_ADDR[9], KB1_PROGRAM_ADDR[10], KB1_PROGRAM_ADDR[11]);
NC1M293_PORT_A_address_reg = DFFE(NC1M293_PORT_A_address, NC1M293_clock_0, , , NC1M293_clock_enable_0);
NC1M293_PORT_B_address = BUS(PC2_ram_rom_addr_reg[0], PC2_ram_rom_addr_reg[1], PC2_ram_rom_addr_reg[2], PC2_ram_rom_addr_reg[3], PC2_ram_rom_addr_reg[4], PC2_ram_rom_addr_reg[5], PC2_ram_rom_addr_reg[6], PC2_ram_rom_addr_reg[7], PC2_ram_rom_addr_reg[8], PC2_ram_rom_addr_reg[9], PC2_ram_rom_addr_reg[10], PC2_ram_rom_addr_reg[11]);
NC1M293_PORT_B_address_reg = DFFE(NC1M293_PORT_B_address, NC1M293_clock_1, , , NC1M293_clock_enable_1);
NC1M293_PORT_A_write_enable = GND;
NC1M293_PORT_A_write_enable_reg = DFFE(NC1M293_PORT_A_write_enable, NC1M293_clock_0, , , NC1M293_clock_enable_0);
NC1M293_PORT_B_write_enable = QC2L2;
NC1M293_PORT_B_write_enable_reg = DFFE(NC1M293_PORT_B_write_enable, NC1M293_clock_1, , , NC1M293_clock_enable_1);
NC1M293_clock_0 = VC1__clk1;
NC1M293_clock_1 = A1L5;
NC1M293_clock_enable_0 = KB1_PROGRAM_ADDR[12];
NC1M293_clock_enable_1 = PC2_ram_rom_addr_reg[12];
NC1M293_PORT_B_data_out = MEMORY(NC1M293_PORT_A_data_in_reg, NC1M293_PORT_B_data_in_reg, NC1M293_PORT_A_address_reg, NC1M293_PORT_B_address_reg, NC1M293_PORT_A_write_enable_reg, NC1M293_PORT_B_write_enable_reg, , , NC1M293_clock_0, NC1M293_clock_1, NC1M293_clock_enable_0, NC1M293_clock_enable_1, , );
NC1M293 = NC1M293_PORT_B_data_out[0];