mcu8951.map.eqn

此示例是8051核加频率计的联合设计,带有8051IP核资料

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--MB1_QALE is CPU8051C1:inst|MCU80512:inst3|m3s018bo:U10|QALE
MB1_QALE = DFFEAS(MB1L370, VC1__clk1, RST,  , CB1_LDV2CK2,  ,  ,  ,  );


--MB1_IDLE is CPU8051C1:inst|MCU80512:inst3|m3s018bo:U10|IDLE
MB1_IDLE = DFFEAS(VCC, VC1__clk1, RST,  ,  , PB1_L_PCON[0],  ,  , VCC);


--MB1_ALE is CPU8051C1:inst|MCU80512:inst3|m3s018bo:U10|ALE
MB1_ALE = MB1_IDLE # !MB1_QALE;


--F1_Q1[15] is CNT32B:inst10|Q1[15]
F1_Q1[15] = DFFEAS(F1L48, VC1__clk1,  ,  ,  ,  ,  ,  ,  );


--F1_Q1[14] is CNT32B:inst10|Q1[14]
F1_Q1[14] = DFFEAS(F1L45, VC1__clk1,  ,  ,  ,  ,  ,  ,  );


--F1_Q1[13] is CNT32B:inst10|Q1[13]
F1_Q1[13] = DFFEAS(F1L42, VC1__clk1,  ,  ,  ,  ,  ,  ,  );


--F1_Q1[12] is CNT32B:inst10|Q1[12]
F1_Q1[12] = DFFEAS(F1L39, VC1__clk1,  ,  ,  ,  ,  ,  ,  );


--F1_Q1[11] is CNT32B:inst10|Q1[11]
F1_Q1[11] = DFFEAS(F1L36, VC1__clk1,  ,  ,  ,  ,  ,  ,  );


--F1_Q1[10] is CNT32B:inst10|Q1[10]
F1_Q1[10] = DFFEAS(F1L33, VC1__clk1,  ,  ,  ,  ,  ,  ,  );


--MB1_PORT3_SFR[7] is CPU8051C1:inst|MCU80512:inst3|m3s018bo:U10|PORT3_SFR[7]
MB1_PORT3_SFR[7] = DFFEAS(MB1L362, VC1__clk1, RST,  , MB1L358,  ,  ,  ,  );


--MB1_NRD is CPU8051C1:inst|MCU80512:inst3|m3s018bo:U10|NRD
MB1_NRD = DFFEAS(MB1L151, VC1__clk1,  ,  , MB1L147,  ,  ,  ,  );


--MB1_OD[7] is CPU8051C1:inst|MCU80512:inst3|m3s018bo:U10|OD[7]
MB1_OD[7] = !MB1_PORT3_SFR[7] & MB1_NRD;


--MB1_NWR is CPU8051C1:inst|MCU80512:inst3|m3s018bo:U10|NWR
MB1_NWR = DFFEAS(MB1L156, VC1__clk1,  ,  , MB1L147,  ,  ,  ,  );


--MB1_PORT3_SFR[6] is CPU8051C1:inst|MCU80512:inst3|m3s018bo:U10|PORT3_SFR[6]
MB1_PORT3_SFR[6] = DFFEAS(MB1L354, VC1__clk1, RST,  , MB1L358,  ,  ,  ,  );


--MB1_OD[6] is CPU8051C1:inst|MCU80512:inst3|m3s018bo:U10|OD[6]
MB1_OD[6] = MB1_NWR & !MB1_PORT3_SFR[6];


--RB1_TSEND is CPU8051C1:inst|MCU80512:inst3|m3s028bo:U15|TSEND
RB1_TSEND = DFFEAS(RB1L321, VC1__clk1,  ,  ,  ,  ,  , !K1_CLEAR,  );


--RB1_L_SCON[6] is CPU8051C1:inst|MCU80512:inst3|m3s028bo:U15|L_SCON[6]
RB1_L_SCON[6] = DFFEAS(VCC, VC1__clk1,  ,  , RB1L126, RB1L143,  ,  , VCC);


--RB1_L_SCON[7] is CPU8051C1:inst|MCU80512:inst3|m3s028bo:U15|L_SCON[7]
RB1_L_SCON[7] = DFFEAS(RB1L144, VC1__clk1,  ,  , RB1L126,  ,  ,  ,  );


--RB1L161 is CPU8051C1:inst|MCU80512:inst3|m3s028bo:U15|MODE0~0
RB1L161 = RB1_L_SCON[6] # RB1_L_SCON[7];


--RB1_TXCLK is CPU8051C1:inst|MCU80512:inst3|m3s028bo:U15|TXCLK
RB1_TXCLK = DFFEAS(RB1L334, VC1__clk1,  ,  ,  ,  ,  ,  ,  );


--RB1_RCV is CPU8051C1:inst|MCU80512:inst3|m3s028bo:U15|RCV
RB1_RCV = DFFEAS(RB1L200, VC1__clk1,  ,  ,  ,  ,  ,  ,  );


--MB1L162 is CPU8051C1:inst|MCU80512:inst3|m3s018bo:U10|OD[1]~285
MB1L162 = RB1_TSEND & !RB1L161 & RB1_TXCLK # !RB1_TSEND & (!RB1L161 & RB1_TXCLK # !RB1_RCV);


--MB1_PORT3_SFR[1] is CPU8051C1:inst|MCU80512:inst3|m3s018bo:U10|PORT3_SFR[1]
MB1_PORT3_SFR[1] = DFFEAS(MB1L329, VC1__clk1, RST,  , MB1L358,  ,  ,  ,  );


--RB1_TXLASTBIT is CPU8051C1:inst|MCU80512:inst3|m3s028bo:U15|TXLASTBIT
RB1_TXLASTBIT = DFFEAS(RB1L356, VC1__clk1,  ,  , RB1L352,  ,  ,  ,  );


--JC1_DAT[0] is CPU8051C1:inst|MCU80512:inst3|m3s028bo:U15|m3s030bo:U9|DAT[0]
JC1_DAT[0] = DFFEAS(JC1L11, VC1__clk1,  ,  , JC1L7,  ,  , !K1_CLEAR,  );


--RB1_DATAEN is CPU8051C1:inst|MCU80512:inst3|m3s028bo:U15|DATAEN
RB1_DATAEN = DFFEAS(RB1L30, VC1__clk1,  ,  ,  ,  ,  ,  ,  );


--MB1L165 is CPU8051C1:inst|MCU80512:inst3|m3s018bo:U10|OD[1]~286
MB1L165 = RB1_TXLASTBIT # JC1_DAT[0] & RB1_DATAEN # !RB1_TSEND;


--MB1L168 is CPU8051C1:inst|MCU80512:inst3|m3s018bo:U10|OD[1]~287
MB1L168 = !MB1_PORT3_SFR[1] & (MB1L162 # RB1L161 & MB1L165);


--MB1_PORT3_SFR[0] is CPU8051C1:inst|MCU80512:inst3|m3s018bo:U10|PORT3_SFR[0]
MB1_PORT3_SFR[0] = DFFEAS(MB1L324, VC1__clk1, RST,  , MB1L358,  ,  ,  ,  );


--MB1L159 is CPU8051C1:inst|MCU80512:inst3|m3s018bo:U10|OD[0]~288
MB1L159 = !MB1_PORT3_SFR[0] & (JC1_DAT[0] # RB1L161 # !RB1_TSEND);


--V1_dffs[9] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_shiftreg32:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[9]
V1_dffs[9] = DFFEAS(V1L50, J2L8,  ,  ,  ,  ,  ,  ,  );


--V1_dffs[6] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_shiftreg32:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[6]
V1_dffs[6] = DFFEAS(V1L35, J2L8,  ,  ,  ,  ,  ,  ,  );


--V1_dffs[3] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_shiftreg32:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[3]
V1_dffs[3] = DFFEAS(V1L20, J2L8,  ,  ,  ,  ,  ,  ,  );


--U1L1 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|XOR3:inst33|1~13
U1L1 = V1_dffs[9] $ V1_dffs[6] $ V1_dffs[3];


--B1_inst19 is CPU8051C1:inst|inst19
B1_inst19 = DFFEAS(B1L24, B1_inst9,  ,  ,  ,  ,  ,  ,  );


--J2_inst10 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|inst10
J2_inst10 = DFFEAS(VCC, AB1_modulus_trigger, !N1_inst,  ,  ,  ,  ,  ,  );


--J2L8 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|inst15~8
J2L8 = B1_inst19 & !J2_inst10;


--V1_dffs[1] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_shiftreg32:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[1]
V1_dffs[1] = DFFEAS(V1L10, J2L8,  ,  ,  ,  ,  ,  ,  );


--V1_dffs[4] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_shiftreg32:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[4]
V1_dffs[4] = DFFEAS(V1L25, J2L8,  ,  ,  ,  ,  ,  ,  );


--V1_dffs[8] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_shiftreg32:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[8]
V1_dffs[8] = DFFEAS(V1L45, J2L8,  ,  ,  ,  ,  ,  ,  );


--U2_1 is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|XOR3:inst34|1
U2_1 = V1_dffs[1] $ V1_dffs[4] $ V1_dffs[8];


--V1_dffs[23] is CPU8051C1:inst|FPGA1C:inst|FPGA1C:inst1|lpm_shiftreg32:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[23]
V1_dffs[23] = DFFEAS(V1L120, J2L8,  ,  ,  ,  ,  ,  ,  );


--A1L6 is altera_internal_jtag~TDO
A1L6 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , H1L20);

--A1L7 is altera_internal_jtag~TMSUTAP
A1L7 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , H1L20);

--A1L5 is altera_internal_jtag~TCKUTAP
A1L5 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , H1L20);

--altera_internal_jtag is altera_internal_jtag
altera_internal_jtag = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , H1L20);


--VC1__clk1 is PLL200:inst7|altpll:altpll_component|_clk1
VC1__clk1 = PLL.CLK1(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLK), .INCLK());


--K1_CLEAR is CPU8051C1:inst|MCU80512:inst3|CLEAR
K1_CLEAR = DFFEAS(K1L4, VC1__clk1, RST,  ,  ,  ,  ,  ,  );


--CB1_STATD[5] is CPU8051C1:inst|MCU80512:inst3|m3s001bo:U1|STATD[5]
CB1_STATD[5] = DFFEAS(VCC, VC1__clk1, RST,  , CB1L59, CB1_SMD,  ,  , VCC);


--MB1L366 is CPU8051C1:inst|MCU80512:inst3|m3s018bo:U10|QALE~78
MB1L366 = !K1_CLEAR & !CB1_STATD[5];


--QB1_OPC[0] is CPU8051C1:inst|MCU80512:inst3|m3s025bo:U14|OPC[0]
QB1_OPC[0] = DFFEAS(QB1L16, VC1__clk1, RST,  , QB1L53,  ,  ,  ,  );


--QB1_OPC[1] is CPU8051C1:inst|MCU80512:inst3|m3s025bo:U14|OPC[1]
QB1_OPC[1] = DFFEAS(QB1L21, VC1__clk1, RST,  , QB1L53,  ,  ,  ,  );


--QB1_OPC[2] is CPU8051C1:inst|MCU80512:inst3|m3s025bo:U14|OPC[2]
QB1_OPC[2] = DFFEAS(QB1L26, VC1__clk1, RST,  , QB1L53,  ,  ,  ,  );


--QB1_OPC[3] is CPU8051C1:inst|MCU80512:inst3|m3s025bo:U14|OPC[3]
QB1_OPC[3] = DFFEAS(QB1L31, VC1__clk1, RST,  , QB1L53,  ,  ,  ,  );


--UB1L46 is CPU8051C1:inst|MCU80512:inst3|m3s004bo:U3|m3s022bo:U1|LODEC~1
UB1L46 = QB1_OPC[0] # QB1_OPC[1] # QB1_OPC[2] # QB1_OPC[3];


--CB1_Q4 is CPU8051C1:inst|MCU80512:inst3|m3s001bo:U1|Q4
CB1_Q4 = DFFEAS(CB1L29, VC1__clk1, RST,  , CB1L92,  ,  ,  ,  );


--CB1_Q5 is CPU8051C1:inst|MCU80512:inst3|m3s001bo:U1|Q5
CB1_Q5 = DFFEAS(CB1L34, VC1__clk1, RST,  , CB1L92,  ,  ,  ,  );


--CB1_CYC[2] is CPU8051C1:inst|MCU80512:inst3|m3s001bo:U1|CYC[2]
CB1_CYC[2] = CB1_Q4 & !CB1_Q5;


--EB1L4 is CPU8051C1:inst|MCU80512:inst3|m3s004bo:U3|AJ~38
EB1L4 = QB1_OPC[1] & !QB1_OPC[3] & !QB1_OPC[2];


--QB1_OPC[5] is CPU8051C1:inst|MCU80512:inst3|m3s025bo:U14|OPC[5]
QB1_OPC[5] = DFFEAS(QB1L41, VC1__clk1, RST,  , QB1L53,  ,  ,  ,  );


--QB1_OPC[6] is CPU8051C1:inst|MCU80512:inst3|m3s025bo:U14|OPC[6]
QB1_OPC[6] = DFFEAS(QB1L46, VC1__clk1, RST,  , QB1L53,  ,  ,  ,  );


--QB1_OPC[7] is CPU8051C1:inst|MCU80512:inst3|m3s025bo:U14|OPC[7]
QB1_OPC[7] = DFFEAS(QB1L51, VC1__clk1, RST,  , QB1L53,  ,  ,  ,  );


--K1L98 is CPU8051C1:inst|MCU80512:inst3|OA[0]~2685
K1L98 = QB1_OPC[5] & QB1_OPC[6] & QB1_OPC[7];


--MB1L182 is CPU8051C1:inst|MCU80512:inst3|m3s018bo:U10|POPMEN~2
MB1L182 = CB1_CYC[2] & K1L98 & (EB1L4 # !UB1L46);