hdb3.txt

实现了用vhdl语言完成在编码过程中的插B功能

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
entity hdb3_v is 
  port(reset,clk: in std_logic; 
          codein: in std_logic_vector(1 downto 0); 
         codeout: out std_logic_vector(1 downto 0);
                b: out std_logic_vector(3 downto 0)); 
end hdb3_v; 
architecture behave of hdb3_v is 
    signal D1,D0       : std_logic_vector(3 downto 0); 
    signal count_1,f: integer range 0 to 1; 
    signal  s :std_logic_vector(3 downto 0);
         
begin 
 process(clk,codein)
  begin    
    if(clk'event and clk='1')then 
       D1(0)<=codein(1); 
       D0(0)<=codein(0); 
       D1(3 downto 1)<=D1(2 downto 0); 
       D0(3 downto 1)<=D0(2 downto 0); 
    end if; 
 end process; 
 process(reset,clk,D1,D0) 
  begin 
      if (reset='1') then 
        count_1<=0;                        ------------count_1是1计数器 
    elsif(clk'event and clk='1')then 
        if(f=1 and (D1(0)='0' and D0(0)='1'))then   ------------输入为1时 
            count_1<=count_1+1;s<=s+1;  
            elsif(D1(0)='1' and D0(0)='1')then ------------输入为V时 
            count_1<=0;
            f<=1;
             else 
                f<=0;
              end if; 
      end if; 
 end process; 
 process(reset,clk) 
  begin 
    if (reset='1') then  
        codeout<="00"; 
    elsif(clk'event and clk='1') then 
        if(count_1=0 and D1(0)='1' and D0(0)='1') then 
            codeout<="10"; 
                       -----------输出为B 
        else  
            codeout<=D1(3)&D0(3); 
        end if; 
    end if; 
 end process; 
b<=s; 
end behave;