seven_seg_impl.vhd

Implement the 7 segment diplay on spartan 3

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity seven_seg_impl is
	
	port
	(
	clk      : in  std_logic;       	         -- 50 MHZ clock
    sw_7_4   : in  std_logic_vector(3 downto 0); -- Digit 3 inputs
    sw_3_0   : in  std_logic_vector(3 downto 0); -- Digit 2 inputs
	btns_3_0 : in  std_logic_vector(3 downto 0); -- Buttons 3 to 0 inputs
    segments : out std_logic_vector(6 downto 0); -- Segment control
    dp_out   : out std_logic;                    -- Decimal point
    an_sel   : out std_logic_vector(3 downto 0)  -- Anode control
	);
	
end seven_seg_impl;

architecture seven_seg_impl of seven_seg_impl is
	component seven_seg_ctrl

		port
		(
		clk      : in  std_logic;                    -- 50 MHZ clock
		rst      : in  std_logic;                    -- reset
		digit0   : in  std_logic_vector(3 downto 0); -- Digit 0 input
		digit1   : in  std_logic_vector(3 downto 0); -- Digit 1 input
		digit2   : in  std_logic_vector(3 downto 0); -- Digit 2 input
		digit3   : in  std_logic_vector(3 downto 0); -- Digit 3 input
		dp_in    : in  std_logic_vector(3 downto 0); -- Decimal point inputs
		segments : out std_logic_vector(6 downto 0); -- Segment Selector
		dp_out   : out std_logic;                    -- Decimal 
		an_sel   : out std_logic_vector(3 downto 0)  -- Anode Select
		);
		
	end component;
	
	
	signal d_one_place, d_zero_place: std_logic_vector(3 downto 0);
	signal sum: std_logic_vector(7 downto 0);
	signal a, b: std_logic_vector(7 downto 0);
	
begin
	instance_of: seven_seg_ctrl
	-- direction of the buttons is not indiciative of the direction of signal flow they are representitive 
	--of the connectoins from the perspective of the instanciated item. left are formal as in the components ports	
	--signals on the right are called external or acutal signals
	
		port map 									--
		(		
		clk=>clk,
		rst=>btns_3_0(3),
		digit3=>sw_7_4,
		digit2=>sw_3_0,
		digit1=>d_one_place,
		digit0=>d_zero_place,
		dp_in=>btns_3_0,
		segments=>segments,
		dp_out=>dp_out,
		an_sel=>an_sel
		);
	
	a <= "0000" & sw_7_4(3 downto 0);
	b <= "0000" & sw_3_0(3 downto 0);
	sum <= std_logic_vector(unsigned(a) + unsigned(b));
	d_one_place <= sum(7 downto 4);
	d_zero_place <= sum(3 downto 0);
	

end seven_seg_impl;