vote7-2.vhd

表决器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY vote7 is
PORT (men:IN std_logic_vector(6 downto 0);
       output: out std_logic);
END vote7;
ARCHITECTURE behave OF vote7 IS
BEGIN
PROCESS(men)
variable temp: integer range 0 to 7;
BEGIN
output<='0' (不需要清零）
for i in 0 to 6 loop
 if(men(i)='1')then
 temp:=temp+1;
else 
temp:=temp;
end if;
end loop;
case temp is
when 0 to 3 => output<='0';
when 4 to 7 => output<='1';
 end case ;
END PROCESS;
 END behave;