multlib.vhd

sparc org, vhdl rtl code

);
end component;

component BLOCK1
port
(
	PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
	POUT,GOUT:out std_logic
);
end component;

component BLOCK1A 
port
(
	PIN2,GIN1,GIN2,PHI:in std_logic;
	GOUT:out std_logic
);
end component;

begin -- Architecture DBLC_0
U1: for I in 0 to 0 generate
	U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 1 to 1 generate
	U21: BLOCK1A port map(PIN(I-1),GIN(I-1),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 2 to 128 generate
	U31: BLOCK1 port map(PIN(I-2),PIN(I-1),GIN(I-1),GIN(I),PHI,POUT(I-2),GOUT(I));
end generate U3;
end DBLC_0;

-- The DBLC-tree: Level 1

library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_1 of DBLC_1_128 is
component INVBLOCK
port
(
	GIN,PHI:in std_logic;
	GOUT:out std_logic
);
end component;

component BLOCK2 
port
(
	PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
	POUT,GOUT:out std_logic
);
end component;

component BLOCK2A 
port
(
	PIN2,GIN1,GIN2,PHI:in std_logic;
	GOUT:out std_logic
);
end component;

begin -- Architecture DBLC_1
U1: for I in 0 to 1 generate
	U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 2 to 3 generate
	U21: BLOCK2A port map(PIN(I-2),GIN(I-2),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 4 to 128 generate
	U31: BLOCK2 port map(PIN(I-4),PIN(I-2),GIN(I-2),GIN(I),PHI,POUT(I-4),GOUT(I));
end generate U3;
end DBLC_1;

-- The DBLC-tree: Level 2

library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_2 of DBLC_2_128 is
component INVBLOCK
port
(
	GIN,PHI:in std_logic;
	GOUT:out std_logic
);
end component;

component BLOCK1
port
(
	PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
	POUT,GOUT:out std_logic
);
end component;

component BLOCK1A 
port
(
	PIN2,GIN1,GIN2,PHI:in std_logic;
	GOUT:out std_logic
);
end component;

begin -- Architecture DBLC_2
U1: for I in 0 to 3 generate
	U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 4 to 7 generate
	U21: BLOCK1A port map(PIN(I-4),GIN(I-4),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 8 to 128 generate
	U31: BLOCK1 port map(PIN(I-8),PIN(I-4),GIN(I-4),GIN(I),PHI,POUT(I-8),GOUT(I));
end generate U3;
end DBLC_2;

-- The DBLC-tree: Level 3

library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_3 of DBLC_3_128 is
component INVBLOCK
port
(
	GIN,PHI:in std_logic;
	GOUT:out std_logic
);
end component;

component BLOCK2 
port
(
	PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
	POUT,GOUT:out std_logic
);
end component;

component BLOCK2A 
port
(
	PIN2,GIN1,GIN2,PHI:in std_logic;
	GOUT:out std_logic
);
end component;

begin -- Architecture DBLC_3
U1: for I in 0 to 7 generate
	U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 8 to 15 generate
	U21: BLOCK2A port map(PIN(I-8),GIN(I-8),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 16 to 128 generate
	U31: BLOCK2 port map(PIN(I-16),PIN(I-8),GIN(I-8),GIN(I),PHI,POUT(I-16),GOUT(I));
end generate U3;
end DBLC_3;

-- The DBLC-tree: Level 4

library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_4 of DBLC_4_128 is
component INVBLOCK
port
(
	GIN,PHI:in std_logic;
	GOUT:out std_logic
);
end component;

component BLOCK1
port
(
	PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
	POUT,GOUT:out std_logic
);
end component;

component BLOCK1A 
port
(
	PIN2,GIN1,GIN2,PHI:in std_logic;
	GOUT:out std_logic
);
end component;

begin -- Architecture DBLC_4
U1: for I in 0 to 15 generate
	U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 16 to 31 generate
	U21: BLOCK1A port map(PIN(I-16),GIN(I-16),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 32 to 128 generate
	U31: BLOCK1 port map(PIN(I-32),PIN(I-16),GIN(I-16),GIN(I),PHI,POUT(I-32),GOUT(I));
end generate U3;
end DBLC_4;

-- The DBLC-tree: Level 5

library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_5 of DBLC_5_128 is
component INVBLOCK
port
(
	GIN,PHI:in std_logic;
	GOUT:out std_logic
);
end component;

component BLOCK2 
port
(
	PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
	POUT,GOUT:out std_logic
);
end component;

component BLOCK2A 
port
(
	PIN2,GIN1,GIN2,PHI:in std_logic;
	GOUT:out std_logic
);
end component;

begin -- Architecture DBLC_5
U1: for I in 0 to 31 generate
	U11: INVBLOCK port map(GIN(I),PHI,GOUT(I));
end generate U1;
U2: for I in 32 to 63 generate
	U21: BLOCK2A port map(PIN(I-32),GIN(I-32),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 64 to 128 generate
	U31: BLOCK2 port map(PIN(I-64),PIN(I-32),GIN(I-32),GIN(I),PHI,POUT(I-64),GOUT(I));
end generate U3;
end DBLC_5;

-- The DBLC-tree: Level 6

library ieee;
use ieee.std_logic_1164.all;
architecture DBLC_6 of DBLC_6_128 is
component BLOCK1
port
(
	PIN1,PIN2,GIN1,GIN2,PHI:in std_logic;
	POUT,GOUT:out std_logic
);
end component;

component BLOCK1A 
port
(
	PIN2,GIN1,GIN2,PHI:in std_logic;
	GOUT:out std_logic
);
end component;

begin -- Architecture DBLC_6
	GOUT(0 to 63) <= GIN(0 to 63);
U2: for I in 64 to 127 generate
	U21: BLOCK1A port map(PIN(I-64),GIN(I-64),GIN(I),PHI,GOUT(I));
end generate U2;
U3: for I in 128 to 128 generate
	U31: BLOCK1 port map(PIN(I-128),PIN(I-64),GIN(I-64),GIN(I),PHI,POUT(I-128),GOUT(I));
end generate U3;
end DBLC_6;

library ieee;
use ieee.std_logic_1164.all;
architecture XORSTAGE of XORSTAGE_128 is
component XXOR1
port
(
	A,B,GIN,PHI:in std_logic;
	SUM:out std_logic
);
end component;
component XXOR2
port
(
	A,B,GIN,PHI:in std_logic;
	SUM:out std_logic
);
end component;
component BLOCK2A 
port
(
	PIN2,GIN1,GIN2,PHI:in std_logic;
	GOUT:out std_logic
);
end component;

begin -- XORSTAGE
U2:for I in 0 to 63 generate
	U22: XXOR1 port map(A(I),B(I),CARRY(I),PHI,SUM(I));
end generate U2;
U3:for I in 64 to 127 generate
	U33: XXOR2 port map(A(I),B(I),CARRY(I),PHI,SUM(I));
end generate U3;
U1: BLOCK2A port map(PBIT,CARRY(0),CARRY(128),PHI,COUT);
end XORSTAGE;

-- The DBLC-tree: All levels encapsulated

library ieee;
use ieee.std_logic_1164.all;
architecture DBLCTREE of DBLCTREE_128 is
component DBLC_0_128
port
(
	PIN: in std_logic_vector(0 to 127);
	GIN: in std_logic_vector(0 to 128);
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 126);
	GOUT: out std_logic_vector(0 to 128)
);
end component;

component DBLC_1_128
port
(
	PIN: in std_logic_vector(0 to 126);
	GIN: in std_logic_vector(0 to 128);
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 124);
	GOUT: out std_logic_vector(0 to 128)
);
end component;

component DBLC_2_128
port
(
	PIN: in std_logic_vector(0 to 124);
	GIN: in std_logic_vector(0 to 128);
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 120);
	GOUT: out std_logic_vector(0 to 128)
);
end component;

component DBLC_3_128
port
(
	PIN: in std_logic_vector(0 to 120);
	GIN: in std_logic_vector(0 to 128);
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 112);
	GOUT: out std_logic_vector(0 to 128)
);
end component;

component DBLC_4_128
port
(
	PIN: in std_logic_vector(0 to 112);
	GIN: in std_logic_vector(0 to 128);
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 96);
	GOUT: out std_logic_vector(0 to 128)
);
end component;

component DBLC_5_128
port
(
	PIN: in std_logic_vector(0 to 96);
	GIN: in std_logic_vector(0 to 128);
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 64);
	GOUT: out std_logic_vector(0 to 128)
);
end component;

component DBLC_6_128
port
(
	PIN: in std_logic_vector(0 to 64);
	GIN: in std_logic_vector(0 to 128);
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 0);
	GOUT: out std_logic_vector(0 to 128)
);
end component;

signal INTPROP_0: std_logic_vector(0 to 126);
signal INTGEN_0: std_logic_vector(0 to 128);
signal INTPROP_1: std_logic_vector(0 to 124);
signal INTGEN_1: std_logic_vector(0 to 128);
signal INTPROP_2: std_logic_vector(0 to 120);
signal INTGEN_2: std_logic_vector(0 to 128);
signal INTPROP_3: std_logic_vector(0 to 112);
signal INTGEN_3: std_logic_vector(0 to 128);
signal INTPROP_4: std_logic_vector(0 to 96);
signal INTGEN_4: std_logic_vector(0 to 128);
signal INTPROP_5: std_logic_vector(0 to 64);
signal INTGEN_5: std_logic_vector(0 to 128);
begin -- Architecture DBLCTREE
U_0: DBLC_0_128 port map(PIN=>PIN,GIN=>GIN,PHI=>PHI,POUT=>INTPROP_0,GOUT=>INTGEN_0);
U_1: DBLC_1_128 port map(PIN=>INTPROP_0,GIN=>INTGEN_0,PHI=>PHI,POUT=>INTPROP_1,GOUT=>INTGEN_1);
U_2: DBLC_2_128 port map(PIN=>INTPROP_1,GIN=>INTGEN_1,PHI=>PHI,POUT=>INTPROP_2,GOUT=>INTGEN_2);
U_3: DBLC_3_128 port map(PIN=>INTPROP_2,GIN=>INTGEN_2,PHI=>PHI,POUT=>INTPROP_3,GOUT=>INTGEN_3);
U_4: DBLC_4_128 port map(PIN=>INTPROP_3,GIN=>INTGEN_3,PHI=>PHI,POUT=>INTPROP_4,GOUT=>INTGEN_4);
U_5: DBLC_5_128 port map(PIN=>INTPROP_4,GIN=>INTGEN_4,PHI=>PHI,POUT=>INTPROP_5,GOUT=>INTGEN_5);
U_6: DBLC_6_128 port map(PIN=>INTPROP_5,GIN=>INTGEN_5,PHI=>PHI,POUT=>POUT,GOUT=>GOUT);
end DBLCTREE;

library ieee;
use ieee.std_logic_1164.all;
architecture DBLCADDER of DBLCADDER_128_128 is
component PRESTAGE_128
port
(
	A: in std_logic_vector(0 to 127);
	B: in std_logic_vector(0 to 127);
	CIN: in std_logic;
	PHI: in std_logic;
	POUT: out std_logic_vector(0 to 127);
	GOUT: out std_logic_vector(0 to 128)
);
end component;

component DBLCTREE_128
port
(
	PIN:in std_logic_vector(0 to 127);
	GIN:in std_logic_vector(0 to 128);
	PHI:in std_logic;
	GOUT:out std_logic_vector(0 to 128);
	POUT:out std_logic_vector(0 to 0)
);
end component;

component XORSTAGE_128
port
(
	A: in std_logic_vector(0 to 127);
	B: in std_logic_vector(0 to 127);
	PBIT: in std_logic;
	PHI: in std_logic;
	CARRY: in std_logic_vector(0 to 128);
	SUM: out std_logic_vector(0 to 127);
	COUT: out std_logic
);
end component;

signal INTPROP: std_logic_vector(0 to 127);
signal INTGEN: std_logic_vector(0 to 128);
signal PBIT:std_logic_vector(0 to 0);
signal CARRY: std_logic_vector(0 to 128);

begin -- Architecture DBLCADDER

U1: PRESTAGE_128 port map(OPA,OPB,CIN,PHI,INTPROP,INTGEN);
U2: DBLCTREE_128 port map(INTPROP,INTGEN,PHI,CARRY,PBIT);
U3: XORSTAGE_128 port map(OPA(0 to 127),OPB(0 to 127),PBIT(0),PHI,CARRY(0 to 128),SUM,COUT);
end DBLCADDER;
------------------------------------------------------------
-- END: Architectures used with the DBLC adder
------------------------------------------------------------

--
-- Modgen multiplier created Fri Aug 16 14:49:18 2002
--
------------------------------------------------------------
-- START: Multiplier Entitiy
------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use work.leon_iface.all;
entity MULTIPLIER_18_18 is
port
(
	MULTIPLICAND: in std_logic_vector(0 to 17);
	MULTIPLIER: in std_logic_vector(0 to 17);
	PHI: in clk_type;
	holdn: in std_logic;
	RESULT: out std_logic_vector(0 to 63)
);
end MULTIPLIER_18_18;
------------------------------------------------------------
-- End: Multiplier Entitiy
------------------------------------------------------------
------------------------------------------------------------
-- START: Top entity
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.leon_iface.all;
entity MUL_17_17 is
  port(clk : in clk_type;
       holdn: in std_logic;
       X: in std_logic_vector(16 downto 0);
       Y: in std_logic_vector(16 downto 0);
       P: out std_logic_vector(33 downto 0));
end MUL_17_17;

architecture A of MUL_17_17 is
  component MULTIPLIER_18_18
    port(MULTIPLICAND: in std_logic_vector(0 to 17);
         MULTIPLIER: in std_logic_vector(0 to 17);
         PHI: in clk_type;
	 holdn: in std_logic;
         RESULT: out std_logic_vector(0 to 63));
  end component;
  signal A: std_logic_vector(0 to 17);
  signal B: std_logic_vector(0 to 17);
  signal Q: std_logic_vector(0 to 63);
begin
  U1: MULTIPLIER_18_18 port map(A,B,CLK, holdn, Q);
  -- std_logic_vector reversals to incorporate decreasing vectors
  A(0) <= X(0);
  A(1) <= X(1);
  A(2) <= X(2);
  A(3) <= X(3);
  A(4) <= X(4);
  A(5) <= X(5);
  A(6) <= X(6);
  A(7) <= X(7);
  A(8) <= X(8);
  A(9) <= X(9);
  A(10) <= X(10);
  A(11) <= X(11);
  A(12) <= X(12);
  A(13) <= X(13);
  A(14) <= X(14);
  A(15) <= X(15);
  A(16) <= X(16);
  A(17) <= X(16);
  B(0) <= Y(0);
  B(1) <= Y(1);
  B(2) <= Y(2);
  B(3) <= Y(3);
  B(4) <= Y(4);
  B(5) <= Y(5);
  B(6) <= Y(6);
  B(7) <= Y(7);
  B(8) <= Y(8);
  B(9) <= Y(9);
  B(10) <= Y(10);
  B(11) <= Y(11);
  B(12) <= Y(12);
  B(13) <= Y(13);
  B(14) <= Y(14);
  B(15) <= Y(15);
  B(16) <= Y(16);