pci_oc.vhd

sparc org, vhdl rtl code

----------------------------------------------------------------------------
--  This file is a part of the LEON VHDL model
--  Copyright (C) 2003 Gaisler Research
--
--  This library is free software; you can redistribute it and/or
--  modify it under the terms of the GNU Lesser General Public
--  License as published by the Free Software Foundation; either
--  version 2 of the License, or (at your option) any later version.
--
--  See the file COPYING.LGPL for the full details of the license.
----------------------------------------------------------------------------
-- Entity: 	pci_oc
-- File:	pci_oc.vhd
-- Description:	Backend for Opencores PCI_IF
-- Author:     	Daniel Hedberg, Gaisler Research
------------------------------------------------------------------------------
--  ReadMe.txt
--  This backend enables access from PCI to AHB and vice-versa. The address
--  mappings are as follows:
--  
--  PCI to AHB access
--
--  BAR0 (MEM area - 4KB)
--
--  0x000 - 0x0FF	PCI conf. space
--  0x100 - 0x1F0	Opencores device specific conf. space
--  
--  BAR1 (MEM area - 1 MB)
--  
--  PCI				AHB
--  0x00000 - 0xFFFFC		0x[000]00000 - 0x[000]FFFFC
--  
--  Values within [default] are configurable in Opencores device specific
--  conf. space.
--  EXAMPLE: How to map an access to AHB address 0x4000_1000?
--  Write 0x4 to P_IMG_CTRL1 reg at 0x110 to enable translation
--  Write 0x4000_1000 to P_TA1 reg at 0x11C
--  For further information refer to Opencores specification
--  
--  AHB to PCI access
--  
--  AHB                                   PCI
--  0xA000_0000 - 0xA000_FFFC             0x0000 - 0xFFFC (I/O access)
--  0xA001_0000 - 0xA001_01F0 (Read only) Opencores device specific conf. space
--  0xC000_0000 - 0xFFFF_FFFC             0xC000_0000 - 0xFFFF_FFFC (MEM access)
--
-- 
--  How to configure the verilog core (all.v)
--  
--  FIFO implementaion: To get an implemention with flip-flops instead of RAMB4
--  comment the lines marked with "//comment for flip-flops"
--
--  To alter default values for how Wishbone addresses are mapped on PCI 16195
--  edit line 16195 to 16221 and 349 to 357
--
-----------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use work.amba.all;
use work.ambacomp.all;
use work.leon_iface.all;

entity pci_oc is
   port (
      rst  : in  std_logic;
      clk  : in  std_logic;
      pci_clk : in std_logic;
      ahbsi : in  ahb_slv_in_type;
      ahbso : out ahb_slv_out_type;
      ahbmi : in  ahb_mst_in_type;
      ahbmo : out ahb_mst_out_type;
      apbi  : in  apb_slv_in_type;
      apbo  : out apb_slv_out_type;
      pcio  : out pci_out_type;
      pcii  : in  pci_in_type;
      irq   : out std_logic
      );
end;

architecture rtl of pci_oc is

type wb_mst_in_type is record
  mdat_i : std_logic_vector(31 downto 0);      -- binary data bus
  rty_i  : std_logic;
  ack_i  : std_logic;                          -- data available
end record;                                                            
                                                                           
type wb_mst_out_type is record
  adr_o  : std_logic_vector(31 downto 0); 	-- address bus (byte) 
  mdat_o : std_logic_vector(31 downto 0); 	-- binary data bus    
  we_o   : std_logic;
  stb_o  : std_logic;
  cab_o  : std_logic;
end record;
                                                                           
type wb_slv_in_type is record
  adr_i  : std_logic_vector(31 downto 0);
  sdat_i : std_logic_vector(31 downto 0);
  we_i   : std_logic;
  stb_i  : std_logic;
end record;

type wb_slv_out_type is record 
  ack_o  : std_logic;				-- data available 
  rty_o  : std_logic;
  sdat_o : std_logic_vector(31 downto 0);	-- binary data bus    
end record;            

  type ahbslv_state_type is (idle, strobe, respond, rty, doreturn);
  type ahbmst_state_type is (idle, req, respond);


  type ahbslv_reg_type is record
                     hresp      : std_logic_vector(1 downto 0);
                     hready     : std_logic;
                     adr_o      : std_logic_vector(31 downto 0);
                     hrdata     : std_logic_vector(31 downto 0);
                     mdat_o     : std_logic_vector(31 downto 0);
                     mdat_i     : std_logic_vector(31 downto 0);
                     ack_i      : std_logic;
                     rty_i      : std_logic;
                     we_o       : std_logic;
                     hburst     : std_logic_vector(2 downto 0);
                     htrans     : std_logic_vector(1 downto 0);
                   end record;

  type ahbmst_reg_type is record
                     adr_i       : std_logic_vector(31 downto 0);
                     ack_o       : std_logic;
                     sdat_i      : std_logic_vector(31 downto 0);

                   end record;

  type wb_reg_type is record
                     stb_i     : std_logic;
                     we_i      : std_logic;
                     cab_o     : std_logic;
                   end record;

  type reg_type is record
                     ahbslv_state   : ahbslv_state_type;
                     ahbmst_state   : ahbmst_state_type;
                     ahbslv         : ahbslv_reg_type;
                     ahbmst         : ahbmst_reg_type;
                     rdata          : std_logic_vector(31 downto 0);
                     wb             : wb_reg_type;
  --                   AHB2WBCtrl     : std_logic_vector(31 downto 0); --31:29=WB_TA,0=WB_TA enable,
                   end record;

  signal r, rin : reg_type;
  signal highbits : std_logic_vector(31 downto 0);
  signal lowbits : std_logic_vector(31 downto 0);
  signal occlk : std_logic;
  signal ocrst : std_logic;

  signal cbe_en : std_logic_vector(3 downto 0);
  signal wbmi : wb_mst_in_type;
  signal wbmo : wb_mst_out_type;
  signal wbsi : wb_slv_in_type;
  signal wbso : wb_slv_out_type;

  signal dmai : ahb_dma_in_type;
  signal dmao : ahb_dma_out_type;


  component pci_bridge32
    port (
      PCI_CLK_i : in std_logic;
      PCI_AD_oe_o : out std_logic_vector(31 downto 0);
      PCI_AD_i : in std_logic_vector(31 downto 0);
      PCI_AD_o : out std_logic_vector(31 downto 0);
      PCI_CBE_oe_o : out std_logic_vector(3 downto 0);
      PCI_CBE_i : in std_logic_vector(3 downto 0);
      PCI_CBE_o : out std_logic_vector(3 downto 0);
      PCI_RST_oe_o : out std_logic;
      PCI_RST_i : in std_logic;
      PCI_RST_o : out std_logic;
      PCI_INTA_oe_o : out std_logic;
      PCI_INTA_i : in std_logic;
      PCI_INTA_o : out std_logic;
      PCI_REQ_oe_o : out std_logic;
      PCI_REQ_o : out std_logic;
      PCI_GNT_i: in std_logic;
      PCI_FRAME_oe_o : out std_logic;
      PCI_FRAME_i : in std_logic;
      PCI_FRAME_o : out std_logic;
      PCI_IRDY_oe_o : out std_logic;
      PCI_IRDY_i : in std_logic;
      PCI_IRDY_o : out std_logic;
      PCI_IDSEL_i: in std_logic;
      PCI_DEVSEL_oe_o : out std_logic;
      PCI_DEVSEL_i : in std_logic;
      PCI_DEVSEL_o : out std_logic;
      PCI_TRDY_oe_o : out std_logic;
      PCI_TRDY_i : in std_logic;
      PCI_TRDY_o : out std_logic;
      PCI_STOP_oe_o : out std_logic;
      PCI_STOP_i : in std_logic;
      PCI_STOP_o : out std_logic;
      PCI_PAR_oe_o : out std_logic;
      PCI_PAR_i : in std_logic;
      PCI_PAR_o : out std_logic;
      PCI_PERR_oe_o : out std_logic;
      PCI_PERR_i : in std_logic;
      PCI_PERR_o : out std_logic;
      PCI_SERR_oe_o : out std_logic;
      PCI_SERR_o : out std_logic;

      WB_CLK_I: in std_logic;
      WB_RST_I: in std_logic;
      WB_RST_O: out std_logic;
      WB_INT_I: in std_logic;
      WB_INT_O: out std_logic;

    -- WISHBONE slave interface
      WBS_ADR_I: in std_logic_vector(31 downto 0);
      WBS_DAT_I: in std_logic_vector(31 downto 0);
      WBS_DAT_O: out std_logic_vector(31 downto 0);
      WBS_SEL_I: in std_logic_vector(3 downto 0);
      WBS_CYC_I: in std_logic;
      WBS_STB_I: in std_logic;
      WBS_WE_I: in std_logic;
      WBS_CAB_I: in std_logic;
      WBS_ACK_O: out std_logic;
      WBS_RTY_O: out std_logic;
      WBS_ERR_O: out std_logic;

    -- WISHBONE master interface
      WBM_ADR_O: out std_logic_vector(31 downto 0);
      WBM_DAT_I: in std_logic_vector(31 downto 0);
      WBM_DAT_O: out std_logic_vector(31 downto 0);
      WBM_SEL_O: out std_logic_vector(3 downto 0);
      WBM_CYC_O: out std_logic;
      WBM_STB_O: out std_logic;
      WBM_WE_O: out std_logic;
      WBM_CAB_O: out std_logic;
      WBM_ACK_I: in std_logic;
      WBM_RTY_I: in std_logic;
      WBM_ERR_I: in std_logic

    );
  end component;

begin

  lowbits <= (others => '0');
  highbits <= (others => '1');
  comb: process (r, ahbsi, wbmi, rst, cbe_en,
                 ahbmi, wbsi, dmao)
    variable v : reg_type;
    variable vstb_o, vstart : std_logic;
    variable vprdata : std_logic_vector(31 downto 0);
--    variable vAHB_TA : std_logic_vector(31 downto 29);
--    variable vAHB_TA_enable : boolean;
  begin  -- process comb
    v := r;
    vstb_o  := '0';
    v.ahbslv.hready := '1';
--    v.wb.cab_o      := '0';
--    vAHB_TA       := r.AHB2WBCtrl(31 downto 29);
--    if r.AHB2WBCtrl(0) = '1' then
--      vAHB_TA_enable := true;
--    else
--      vAHB_TA_enable := false;
--    end if;

    case r.ahbslv_state is

      when idle   =>
        v.ahbslv.ack_i := '0';
--         if not r.ahbslv.hburst = "001" then
--           v.wb.cab_o := '0';