📄 dcache.vhd
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for i in DSETS-1 downto 0 loop
if DSNOOP and DSNOOP_FAST then
-- pragma translate_off
if not is_x(rh.taddr) then
-- pragma translate_on
snoophit(i) := rh.hit(conv_integer(rh.taddr))(i);
-- pragma translate_off
end if;
-- pragma translate_on
end if;
if (dcramov.dtramout(i).tag = dci.maddress(TAG_HIGH downto TAG_LOW))
then hitv(i) := '1'; end if; -- not r.flush; set := i; end if;
validrawv(i) := hitv(i) and (not r.flush) and (not snoophit(i)) and
genmux(dci.maddress(LINE_HIGH downto LINE_LOW), dcramov.dtramout(i).valid);
validv(i) := validrawv(i);
if (hitv(i) and not snoophit(i)) = '1' then ivalid := ivalid or dcramov.dtramout(i).valid; end if;
snoopval := snoopval and not snoophit(i);
end loop;
hit := orv(hitv) and not r.flush; validraw := orv(validrawv);
valid := orv(validv);
if DSETS > 1 then
for i in DSETS-1 downto 0 loop
if (hitv(i) = '1') then
vset := vset or std_logic_vector(conv_unsigned(i, SETBITS));
end if;
end loop;
set := conv_integer(vset);
else set := 0; end if;
if (dci.dsuen and (not r.holdn)) = '1' then diagset := r.xaddress(TAG_LOW+SETBITS-1 downto TAG_LOW);
else diagset := maddress(TAG_LOW + SETBITS - 1 downto TAG_LOW); end if;
-- pragma translate_off
if not is_x(diagset) then
-- pragma translate_on
case DSETS is
when 1 => ddset := 0;
when 3 => if conv_integer(diagset) < 3 then ddset := conv_integer(diagset); end if;
when others => ddset := conv_integer(diagset);
end case;
-- pragma translate_off
end if;
--pragma translate_on
if ((r.holdn and dci.enaddr) = '1') and (r.dstate = "000") then
v.hit := hit; v.xaddress := dci.maddress;
v.read := dci.read; v.size := dci.size;
v.asi := dci.asi(3 downto 0);
v.signed := dci.signed;
end if;
-- Store buffer
-- wdata := r.wb.data1;
if mcdo.ready = '1' then
v.wb.addr(2) := r.wb.addr(2) or (r.wb.size(0) and r.wb.size(1));
if r.stpend = '1' then
v.stpend := r.req; v.wb.data1 := r.wb.data2;
v.wb.lock := r.wb.lock and r.req;
end if;
end if;
if mcdo.grant = '1' then v.req := r.burst; v.burst := '0'; end if;
if (LOCAL_RAM) then
if ((r.holdn) = '0') or (DEBUG_UNIT and (dci.dsuen = '1')) then
laddr := r.xaddress;
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0') then
laddr := dci.maddress;
else laddr := dci.eaddress; end if;
if (dci.enaddr = '1') and (dci.maddress(31 downto 24) = LOCAL_RAM_START)
then lramen := '1'; end if;
if ((dci.eenaddr or dci.enaddr) = '1') and (laddr(31 downto 24) = LOCAL_RAM_START)
then lramcs := '1'; end if;
end if;
-- main Dcache state machine
case r.dstate is
when "000" => -- Idle state
v.nomds := r.nomds and not eholdn;
if (snoopval = '1') then v.valid := dcramov.dtramout(set).valid;
else v.valid := (others => '0'); end if;
if (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then -- wait for store queue
v.wb.addr := dci.maddress; v.wb.size := dci.size;
v.wb.read := dci.read; v.wb.data1 := dci.edata; v.wb.lock := dci.lock;
v.wb.asi := dci.asi(3 downto 0);
end if;
if (eholdn and (not r.nomds)) = '1' then -- avoid false path through nullify
if dci.asi(3 downto 0) = LASI_DTAG then rdatasel := dtag; end if;
if dci.asi(3 downto 0) = LASI_DDATA then rdatasel := dddata; end if;
end if;
if (dci.enaddr and eholdn and (not r.nomds) and not dci.nullify) = '1' then
case dci.asi(3 downto 0) is
when LASI_ITAG | LASI_IDATA => -- Read/write Icache tags
if ico.flush = '1' then mexc := '1';
else v.dstate := "101"; v.holdn := '0'; end if;
when LASI_IFLUSH => -- flush instruction cache
if dci.read = '0' then iflush := '1'; end if;
when LASI_DFLUSH => -- flush data cache
if dci.read = '0' then flush := '1'; end if;
when LASI_DDATA => -- Read/write Dcache data
if (dci.size /= "10") or (r.flush = '1') then -- only word access is allowed
mexc := '1';
elsif (dci.read = '0') then
dwrite := '1'; ddiagwrite := '1';
end if;
when LASI_DTAG => -- Read/write Dcache tags
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
twrite := '1'; tdiagwrite := '1';
end if;
when others =>
-- setrepl := std_logic_vector(conv_unsigned(set, SETBITS));
if dci.read = '1' then -- read access
if LOCAL_RAM and (lramen = '1') then
lramrd := '1';
elsif (not ((mcdo.dcs(0) = '1')
and ((hit and valid and not forcemiss) = '1')))
then -- read miss
v.holdn := '0'; v.dstate := "001";
if ((r.stpend = '0') or ((mcdo.ready and not r.req) = '1'))
then -- wait for store queue
v.req := '1';
v.burst := dci.size(1) and dci.size(0) and not dci.maddress(2);
end if;
else -- read hit
if (DSETS > 1) and (DCREPLACE = lru) then vl.write := '1'; end if;
end if;
else -- write access
if LOCAL_RAM and (lramen = '1') then
lramwr := '1'; lramrd := '1';
if (dci.size = "11") then v.dstate := "100"; end if; -- double store
elsif (r.stpend = '0') or ((mcdo.ready and not r.req)= '1') then -- wait for store queue
v.req := '1'; v.stpend := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := "100"; end if; -- double store
else -- wait for store queue
v.dstate := "110"; v.holdn := '0';
end if;
if (mcdo.dcs(0) = '1') and ((hit and (dci.size(1) or validraw)) = '1')
then -- write hit
twrite := '1'; dwrite := '1';
if (DSETS > 1) and (DCREPLACE = lru) then vl.write := '1'; end if;
setrepl := std_logic_vector(conv_unsigned(set, SETBITS));
end if;
if (dci.size = "11") then v.xaddress(2) := '1'; end if;
end if;
if (DSETS > 1) then
vl.set := std_logic_vector(conv_unsigned(set, SETBITS));
v.setrepl := std_logic_vector(conv_unsigned(set, SETBITS));
if ((not hit) and (not r.flush)) = '1' then
case DCREPLACE is
when rnd =>
if DCLOCK_BIT = 1 then
if lock(conv_integer(r.rndcnt)) = '0' then v.setrepl := r.rndcnt;
else
v.setrepl := std_logic_vector(conv_unsigned(DSETS-1, SETBITS));
for i in DSETS-1 downto 0 loop
if (lock(i) = '0') and (i>conv_integer(r.rndcnt)) then
v.setrepl := std_logic_vector(conv_unsigned(i, SETBITS));
end if;
end loop;
end if;
else
v.setrepl := r.rndcnt;
end if;
when lru =>
-- pragma translate_off
if not is_x(dci.maddress(OFFSET_HIGH downto OFFSET_LOW)) then
-- pragma translate_on
v.setrepl := lru_set(rl.lru(conv_integer(dci.maddress(OFFSET_HIGH downto OFFSET_LOW))), lock(0 to DSETS-1));
-- pragma translate_off
end if;
-- pragma translate_on
when lrr =>
v.setrepl := (others => '0');
if DCLOCK_BIT = 1 then
if lock(0) = '1' then v.setrepl(0) := '1';
else
v.setrepl(0) := dcramov.dtramout(0).lrr xor dcramov.dtramout(1).lrr;
end if;
else
v.setrepl(0) := dcramov.dtramout(0).lrr xor dcramov.dtramout(1).lrr;
end if;
if v.setrepl(0) = '0' then
v.lrr := not dcramov.dtramout(0).lrr;
else
v.lrr := dcramov.dtramout(0).lrr;
end if;
end case;
end if;
if (DCLOCK_BIT = 1) then
if (hit and lock(set)) = '1' then v.lock := '1';
else v.lock := '0'; end if;
end if;
end if;
end case;
end if;
when "001" => -- read miss, wait for memory data
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
v.nomds := r.nomds and not eholdn;
v.holdn := v.nomds; rdatasel := memory;
for i in 0 to DSETS-1 loop wlock(i) := r.lock; end loop;
for i in 0 to 1 loop wlrr(i) := r.lrr; end loop;
if r.stpend = '0' then
if mcdo.ready = '1' then
mds := r.holdn or r.nomds; v.xaddress(2) := '1'; v.holdn := '1';
if (mcdo.dcs = "01") then
v.hit := mcdo.cache and r.hit; twrite := v.hit;
elsif (mcdo.dcs(1) = '1') then
v.hit := mcdo.cache and (r.hit or not r.asi(2)); twrite := v.hit;
end if;
dwrite := twrite; rdatasel := memory;
mexc := mcdo.mexc;
if r.req = '0' then
if (((dci.enaddr and not mds) = '1') or
((dci.eenaddr and mds and eholdn) = '1')) and (mcdo.dcs(0) = '1') then
v.dstate := "011"; v.holdn := '0';
else v.dstate := "000"; end if;
else v.nomds := '1'; end if;
end if;
v.mexc := mcdo.mexc; v.wb.data2 := mcdo.data;
else
if ((mcdo.ready and not r.req) = '1') then -- wait for store queue
v.burst := r.size(1) and r.size(0) and not r.xaddress(2);
v.wb.addr := r.xaddress; v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress; v.req := '1';
v.wb.lock := dci.lock; v.wb.asi := r.asi;
end if;
end if;
when "011" => -- return from read miss with load pending
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
v.dstate := "000";
when "100" => -- second part of double store cycle
v.dstate := "000";
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
if LOCAL_RAM then laddr := r.xaddress; end if;
if LOCAL_RAM and (r.xaddress(31 downto 24) = LOCAL_RAM_START) then
lramwr := '1';
else
if (mcdo.dcs(0) = '1') and (r.hit = '1') then dwrite := '1'; end if;
v.wb.data2 := dci.edata;
end if;
when "101" => -- icache diag access
rdatasel := icache; v.icenable := '1'; v.holdn := '0';
if ico.diagrdy = '1' then
v.dstate := "011"; v.icenable := '0'; mds := not r.read;
end if;
when "110" => -- wait for store buffer to empty (store access)
edata := dci.edata; -- needed for STD store hit
if ((mcdo.ready and not r.req) = '1') then -- store queue emptied
if (mcdo.dcs(0) = '1') and (r.hit = '1') and (r.size = "11") then -- write hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW); dwrite := '1';
end if;
v.dstate := "000";
v.req := '1'; v.burst := r.size(1) and r.size(0); v.stpend := '1';
v.wb.addr := r.xaddress; v.wb.size := r.size;
v.wb.read := r.read; v.wb.data1 := dci.maddress;
v.wb.lock := dci.lock; v.wb.data2 := dci.edata;
v.wb.asi := r.asi;
if r.size = "11" then v.wb.addr(2) := '0'; end if;
else -- hold cpu until buffer empty
v.holdn := '0';
end if;
when others => v.dstate := "000";
end case;
dsudata := (others => '0');
if DEBUG_UNIT and dci.dsuen = '1' then
if (DSETS > 1) then
-- pragma translate_off
if not is_x(r.xaddress) then
-- pragma translate_on
v.dsuset := r.xaddress(TAG_LOW+SETBITS-1 downto TAG_LOW);
-- pragma translate_off
end if;
if not is_x(r.dsuset) then
-- pragma translate_on
rdsuset := conv_integer(r.dsuset);
-- pragma translate_off
end if;
-- pragma translate_on
end if;
case dci.asi(3 downto 0) is
when LASI_ITAG | LASI_IDATA => -- Read/write Icache tags
v.icenable := not ico.diagrdy;
dsudata := ico.diagdata;
when LASI_DTAG =>
if dci.write = '1' then
twrite := not dci.eenaddr; tdiagwrite := '1';
end if;
dsudata(TAG_HIGH downto TAG_LOW) := dcramov.dtramout(rdsuset).tag;
dsudata(DLINE_SIZE -1 downto 0) := dcramov.dtramout(rdsuset).valid;
dsudata(DCTAG_LRRPOS) := dcramov.dtramout(rdsuset).lrr;
dsudata(DCTAG_LOCKPOS) := dcramov.dtramout(rdsuset).lock;
when LASI_DDATA =>
--if (dci.write and r.dsuwren) = '1' then dwrite := '1'; ddiagwrite := '1'; end if;
if (LOCAL_RAM) and (laddr(19 downto 16) = "1111") then
lramwr := dci.write and not dci.eenaddr;
v.lramrd := not lramwr; lramcs := '1';
elsif dci.write = '1' then
dwrite := not dci.eenaddr; ddiagwrite := '1';
end if;
dsudata := dcramov.ddramout(rdsuset).data;
when others =>
end case;
end if;
-- select data to return on read access
-- align if byte/half word read from cache or memory.
rdata := (others => '0'); rdatav := (others => (others => '0'));
align_data := (others => '0'); align_datav := (others => (others => '0'));
maddrlow := maddress(1 downto 0); -- stupid Synopsys VSS bug ...
case rdatasel is
when dddata =>
rdata := dcramov.ddramout(ddset).data;
when dtag =>
rdata(TAG_HIGH downto TAG_LOW) := dcramov.dtramout(ddset).tag;
rdata(DLINE_SIZE -1 downto 0) := dcramov.dtramout(ddset).valid;
rdata(DCTAG_LRRPOS) := dcramov.dtramout(ddset).lrr;
rdata(DCTAG_LOCKPOS) := dcramov.dtramout(ddset).lock;
when icache => rdata := ico.diagdata;
when ddata | memory =>
if DREAD_FAST then
if rdatasel = memory then
case size is
when "00" => -- byte read
case maddrlow is
when "00" =>
rdata(7 downto 0) := mcdo.data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => mcdo.data(31)); end if;
when "01" =>
rdata(7 downto 0) := mcdo.data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => mcdo.data(23)); end if;
when "10" =>
rdata(7 downto 0) := mcdo.data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => mcdo.data(15)); end if;
when others =>
rdata(7 downto 0) := mcdo.data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => mcdo.data(7)); end if;
end case;
when "01" => -- half-word read
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