simulate.v

FPGA控制AD逐点采集信号

module Simulate(Clk,Dout,Dvalid,DClk,AD_A0,AD_RD,AD_CS,CONV_AD,AD_BUSY,AD_DATA,
				Address,Conv,InDots,Integral);
input Clk;
input AD_BUSY;
input[11:0]AD_DATA;
output AD_RD,AD_CS,CONV_AD,AD_A0;

output Dout,Dvalid,DClk;

input[10:0]InDots;
input[4:0]Integral;

output[12:0]Address;
output Conv;


reg AD_RD,AD_CS,CONV_AD;
reg	DClk,Dout,Dvalid;
reg [2:0]DOut_State;
reg [6:0]S_Count;
reg [31:0]AD_D2,AD_D1;
reg [14:0]SendData;
reg AD_D_Flg1,AD_D_Flg2;
reg [2:0]AD_State;

reg [9:0]TemCont;// 产生Conv信号
reg  AD_Flg1,AD_Flg2;// 数据转化标志

//地址信号
reg Conv;
reg [12:0]Address;
reg Clk1;
reg [7:0] Count;// 产生地址转化时钟计数器


//复位寄存器
reg iReset;
reg[1:0]R_Status;

//采样点
wire[10:0]SendData_Num;


wire [9:0] Integral_Count1;


assign AD_A0=0;

assign SendData_Num=InDots;
assign Integral_Count1=Integral*20;

//产生Conv信号使差分模拟数据输出 
always@(negedge iReset or posedge Clk)
begin
        if(!iReset)
        begin
			AD_Flg1<=0;
			TemCont<=10'h0;
			Address<=13'b0;
	   end
	   else   
	   begin
			TemCont <= TemCont+1;
			if(TemCont==(Integral_Count1-25))	
			begin
					AD_Flg1<=1;
			end
			if(TemCont==(Integral_Count1-20))	
			begin
					Conv <=1;	
					if(Address==0)
						Dvalid<=1;					
			end
			if(TemCont==Integral_Count1)
			begin
				TemCont<=0;
				AD_Flg1<=0;
				Dvalid<=0;
				Conv<=0;
				Address<=Address+1;
				if (Address == SendData_Num)	
				begin
					Address<=0;
				end
			end
				
		end		
			
end



//产生AD转化的RD,CS,CONV_AD
always@(negedge iReset or posedge Clk )
begin
	if(!iReset)
	begin
			AD_Flg2<=0;
			AD_D_Flg1<=0;
	end
	else
	begin
			if (AD_Flg1)
				AD_Flg2<=1;
			if(AD_Flg2)
			begin
				 case(AD_State)
				 0:begin
				 		CONV_AD<=1;
						AD_RD<=1;
				 		AD_CS<=1;
				 		AD_State<=AD_State+1;
				   end
				 1:begin
				 		CONV_AD<=0;
				 		AD_State<=AD_State+1;
				   end
				 2:begin
				 		if(AD_BUSY==1)
				 			CONV_AD<=0;
				 		else
				 		begin
				 			AD_State<=AD_State+1;
				 			CONV_AD<=1;
				 		end
				 	end
				 3:begin
						AD_RD<=0;
				 		AD_CS<=0;
				 		AD_State<=AD_State+1;
				 	end
				 4:begin
				 		AD_RD<=1;
						AD_CS<=1;
						AD_D1[11:0]<=AD_DATA;
						AD_D1[15:12]<=4'b0000;
				 		AD_State<=AD_State+1;
				 	end	
				 5:begin
				 		AD_RD<=0;
						AD_CS<=0;
				 		AD_State<=AD_State+1;
				 	end
				 6:begin
				 		AD_RD<=1;
						AD_CS<=1;
						AD_D1[27:16]<=AD_DATA;
						AD_D1[31:28]<=4'b0000;
						AD_D_Flg1<=1;
				 		AD_State<=AD_State+1;
				 	end
				 7:begin
				 		AD_RD<=1;
						AD_CS<=1;
				 		AD_Flg2<=0;
				 		AD_D_Flg1<=0;
				 		AD_State<=0;
				 	end
				endcase
			end
	end
end



//串行输出数据
always@(negedge iReset or posedge Clk)
begin
		if(!iReset)
		begin
			AD_D_Flg2<=0;
		end
		else
		begin
				if(AD_D_Flg1)
					AD_D_Flg2<=1;
				if(AD_D_Flg2)
				begin
					case(DOut_State)
						0:begin
							  DOut_State<=1;
							  AD_D2<=AD_D1;
						  end
						1:begin
							    DClk<=1;
								Dout<=AD_D2[0];
								AD_D2<={1'b0,AD_D2[31:1]};
								S_Count<=S_Count+1;
								DOut_State<=2;
						  end	
						2:begin
								DClk<=0;
								if(S_Count==32)
								begin
									DOut_State<=0;
									S_Count<=0;	
									AD_D_Flg2<=0;
								end
								else
									DOut_State<=1;	
							end		
					  endcase
				end
		end
end


//复位模块
always@(posedge Clk)
begin
	case(R_Status)
	0:begin
		R_Status<=1;
		iReset<=1;
	  end
	1:begin
		R_Status<=2;
		iReset<=1;
	  end
	2:begin
		R_Status<=3;
		iReset<=0;
	  end
	3:begin
		R_Status<=3;
		iReset<=1;
	  end
	endcase
end
endmodule