fpga_port.v

来自「基于FPGA的频率相位可调DDS信号发生器」· Verilog 代码 · 共 86 行

module FPGA_BUS_PORT(clk,cs,wr,rd,data,add,reg1_out,reg2_out,
					clk_out,cs1,wave_out1,DA_clk_out,DA_sleep_out);
input clk,cs,wr,rd;
inout[15:0] data;
input[7:0] add;
output[15:0] reg1_out,reg2_out;
output clk_out;
input cs1;
reg[15:0] data;
output[11:0] wave_out1;
output DA_clk_out,DA_sleep_out;
assign DA_sleep_out=1'b0;
///////////////////////////
reg[15:0] reg0,reg1,reg2;
parameter reg1_add=8'ha5;//寄存器1地址映射到0x30014a00
parameter reg2_add=8'ha6;//寄存器2地址映射到0x30014c00
assign reg1_out=reg1;
assign reg2_out=reg2;
///////////////////////////
wire inter_clk;
clkpll pll1(
	.inclk0(clk),
	.c0(inter_clk));
assign clk_out=clk;
assign DA_clk_out=inter_clk;
///////////////////////////
///////////////////////////方波发生部分
parameter fre_factor_hi_add=8'ha7;
parameter fre_factor_low_add=8'ha8;
reg[15:0] fre_factor_hi;//频率控制字寄存器高位，映射地址0x30014e00
reg[15:0] fre_factor_low;//频率控制字存器低位,映射地址0x30015000
wave_gen_new wave_gen(
		.clk(inter_clk),
		.fre_factor_hi(16'h028f),
		.fre_factor_low(16'h5c29),
		.out1(wave_out1),
		);
///////////////////////////
	

always @(posedge clk)
begin
	if(~cs)
	begin
		case(add)
		reg1_add:
		begin
			if(~wr)
				reg1<=data;
			if(~rd)
				data<=reg1;
		end
		
		reg2_add:
		begin
			if(~wr)
				reg2<=data;
			if(~rd)
				data<=reg2;
		end
		
		fre_factor_hi_add:
		begin
			if(~wr)
				fre_factor_hi<=data;
			if(~rd)
				data<=fre_factor_hi;
		end
		
		fre_factor_low_add:
		begin
			if(~wr)
				fre_factor_low<=data;
			if(~rd)
				data<=fre_factor_low;
		end
		
		default:
			data<=16'hzzzz;
		endcase
	end
	else
		data<=16'hzzzz;
end		

endmodule