adc.tan.rpt

adc0809用FPGA控制的采样非常好用的实例 自己看书后终结的

+-------+--------------+------------+------+-------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To                ; To Clock ;
+-------+--------------+------------+------+-------------------+----------+
; N/A   ; None         ; 2.900 ns   ; EOC  ; current_state.st3 ; CLK      ;
; N/A   ; None         ; 2.900 ns   ; EOC  ; current_state.st2 ; CLK      ;
+-------+--------------+------------+------+-------------------+----------+


+-------------------------------------------------------------------------------+
; tco                                                                           ;
+-------+--------------+------------+----------------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From                 ; To    ; From Clock ;
+-------+--------------+------------+----------------------+-------+------------+
; N/A   ; None         ; 16.800 ns  ; current_state.st3    ; OE    ; CLK        ;
; N/A   ; None         ; 16.300 ns  ; current_state.st4    ; OE    ; CLK        ;
; N/A   ; None         ; 13.900 ns  ; current_state.st1~16 ; START ; CLK        ;
; N/A   ; None         ; 13.200 ns  ; current_state.st1    ; ALE   ; CLK        ;
+-------+--------------+------------+----------------------+-------+------------+


+-------------------------------------------------------------------------------+
; th                                                                            ;
+---------------+-------------+-----------+------+-------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                ; To Clock ;
+---------------+-------------+-----------+------+-------------------+----------+
; N/A           ; None        ; 1.200 ns  ; EOC  ; current_state.st3 ; CLK      ;
; N/A           ; None        ; 1.200 ns  ; EOC  ; current_state.st2 ; CLK      ;
+---------------+-------------+-----------+------+-------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Apr 05 22:05:29 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ADC -c ADC
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Can't find clock settings "clk" in current project -- ignoring clock settings
Info: Clock "CLK" Internal fmax is restricted to 125.0 MHz between source register "current_state.st2" and destination register "current_state.st3"
    Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.300 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_A13; Fanout = 2; REG Node = 'current_state.st2'
            Info: 2: + IC(0.600 ns) + CELL(1.700 ns) = 2.300 ns; Loc. = LC1_A13; Fanout = 2; REG Node = 'current_state.st3'
            Info: Total cell delay = 1.700 ns ( 73.91 % )
            Info: Total interconnect delay = 0.600 ns ( 26.09 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 5.300 ns
                Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 6; CLK Node = 'CLK'
                Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_A13; Fanout = 2; REG Node = 'current_state.st3'
                Info: Total cell delay = 2.800 ns ( 52.83 % )
                Info: Total interconnect delay = 2.500 ns ( 47.17 % )
            Info: - Longest clock path from clock "CLK" to source register is 5.300 ns
                Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 6; CLK Node = 'CLK'
                Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC6_A13; Fanout = 2; REG Node = 'current_state.st2'
                Info: Total cell delay = 2.800 ns ( 52.83 % )
                Info: Total interconnect delay = 2.500 ns ( 47.17 % )
        Info: + Micro clock to output delay of source is 1.100 ns
        Info: + Micro setup delay of destination is 2.500 ns
Info: tsu for register "current_state.st3" (data pin = "EOC", clock pin = "CLK") is 2.900 ns
    Info: + Longest pin to register delay is 5.700 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_84; Fanout = 2; PIN Node = 'EOC'
        Info: 2: + IC(1.700 ns) + CELL(1.200 ns) = 5.700 ns; Loc. = LC1_A13; Fanout = 2; REG Node = 'current_state.st3'
        Info: Total cell delay = 4.000 ns ( 70.18 % )
        Info: Total interconnect delay = 1.700 ns ( 29.82 % )
    Info: + Micro setup delay of destination is 2.500 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 6; CLK Node = 'CLK'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_A13; Fanout = 2; REG Node = 'current_state.st3'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
Info: tco from clock "CLK" to destination pin "OE" through register "current_state.st3" is 16.800 ns
    Info: + Longest clock path from clock "CLK" to source register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 6; CLK Node = 'CLK'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_A13; Fanout = 2; REG Node = 'current_state.st3'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 10.400 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A13; Fanout = 2; REG Node = 'current_state.st3'
        Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC3_A13; Fanout = 1; COMB Node = 'OE~0'
        Info: 3: + IC(2.400 ns) + CELL(5.100 ns) = 10.400 ns; Loc. = PIN_72; Fanout = 0; PIN Node = 'OE'
        Info: Total cell delay = 7.400 ns ( 71.15 % )
        Info: Total interconnect delay = 3.000 ns ( 28.85 % )
Info: th for register "current_state.st3" (data pin = "EOC", clock pin = "CLK") is 1.200 ns
    Info: + Longest clock path from clock "CLK" to destination register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 6; CLK Node = 'CLK'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_A13; Fanout = 2; REG Node = 'current_state.st3'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro hold delay of destination is 1.600 ns
    Info: - Shortest pin to register delay is 5.700 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_84; Fanout = 2; PIN Node = 'EOC'
        Info: 2: + IC(1.700 ns) + CELL(1.200 ns) = 5.700 ns; Loc. = LC1_A13; Fanout = 2; REG Node = 'current_state.st3'
        Info: Total cell delay = 4.000 ns ( 70.18 % )
        Info: Total interconnect delay = 1.700 ns ( 29.82 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Apr 05 22:05:30 2009
    Info: Elapsed time: 00:00:01