adc.map.rpt

adc0809用FPGA控制的采样非常好用的实例 自己看书后终结的

; Total fan-out                   ; 18        ;
; Average fan-out                 ; 0.62      ;
+---------------------------------+-----------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                     ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |ADC                       ; 6 (6)       ; 5            ; 0           ; 23   ; 1 (1)        ; 1 (1)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |ADC                ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------------------------------------------------------------------------+
; State Machine - |ADC|current_state                                                                                    ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; Name              ; current_state.st4 ; current_state.st3 ; current_state.st2 ; current_state.st1 ; current_state.st0 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; current_state.st0 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ;
; current_state.st1 ; 0                 ; 0                 ; 0                 ; 1                 ; 1                 ;
; current_state.st2 ; 0                 ; 0                 ; 1                 ; 0                 ; 1                 ;
; current_state.st3 ; 0                 ; 1                 ; 0                 ; 0                 ; 1                 ;
; current_state.st4 ; 1                 ; 0                 ; 0                 ; 0                 ; 1                 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 5     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------+
; Source assignments for Top-level Entity: |ADC     ;
+----------------+-------+------+-------------------+
; Assignment     ; Value ; From ; To                ;
+----------------+-------+------+-------------------+
; POWER_UP_LEVEL ; Low   ; -    ; current_state.st4 ;
; POWER_UP_LEVEL ; Low   ; -    ; current_state.st3 ;
; POWER_UP_LEVEL ; Low   ; -    ; current_state.st2 ;
; POWER_UP_LEVEL ; Low   ; -    ; current_state.st1 ;
; POWER_UP_LEVEL ; High  ; -    ; current_state.st0 ;
+----------------+-------+------+-------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Apr 05 22:05:16 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ADC -c ADC
Info: Found 2 design units, including 1 entities, in source file ADC.vhd
    Info: Found design unit 1: ADC-behav
    Info: Found entity 1: ADC
Info: Elaborating entity "ADC" for the top level hierarchy
Warning: No clock transition on "REGL[1]" register due to stuck clock or clock enable
Warning: Reduced register "REGL[1]" with stuck clock port to stuck value GND
Warning: No clock transition on "REGL[0]" register due to stuck clock or clock enable
Warning: Reduced register "REGL[0]" with stuck clock port to stuck value GND
Warning: No clock transition on "REGL[2]" register due to stuck clock or clock enable
Warning: Reduced register "REGL[2]" with stuck clock port to stuck value GND
Warning: No clock transition on "REGL[3]" register due to stuck clock or clock enable
Warning: Reduced register "REGL[3]" with stuck clock port to stuck value GND
Warning: No clock transition on "REGL[4]" register due to stuck clock or clock enable
Warning: Reduced register "REGL[4]" with stuck clock port to stuck value GND
Warning: No clock transition on "REGL[5]" register due to stuck clock or clock enable
Warning: Reduced register "REGL[5]" with stuck clock port to stuck value GND
Warning: No clock transition on "REGL[6]" register due to stuck clock or clock enable
Warning: Reduced register "REGL[6]" with stuck clock port to stuck value GND
Warning: No clock transition on "REGL[7]" register due to stuck clock or clock enable
Warning: Reduced register "REGL[7]" with stuck clock port to stuck value GND
Info: State machine "|ADC|current_state" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|ADC|current_state"
Info: Encoding result for state machine "|ADC|current_state"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "current_state.st4"
        Info: Encoded state bit "current_state.st3"
        Info: Encoded state bit "current_state.st2"
        Info: Encoded state bit "current_state.st1"
        Info: Encoded state bit "current_state.st0"
    Info: State "|ADC|current_state.st0" uses code string "00000"
    Info: State "|ADC|current_state.st1" uses code string "00011"
    Info: State "|ADC|current_state.st2" uses code string "00101"
    Info: State "|ADC|current_state.st3" uses code string "01001"
    Info: State "|ADC|current_state.st4" uses code string "10001"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "ADDA" stuck at VCC
    Warning: Pin "LOCK0" stuck at GND
    Warning: Pin "Q[0]" stuck at GND
    Warning: Pin "Q[1]" stuck at GND
    Warning: Pin "Q[2]" stuck at GND
    Warning: Pin "Q[3]" stuck at GND
    Warning: Pin "Q[4]" stuck at GND
    Warning: Pin "Q[5]" stuck at GND
    Warning: Pin "Q[6]" stuck at GND
    Warning: Pin "Q[7]" stuck at GND
Warning: Design contains 8 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "D[0]"
    Warning: No output dependent on input pin "D[1]"
    Warning: No output dependent on input pin "D[2]"
    Warning: No output dependent on input pin "D[3]"
    Warning: No output dependent on input pin "D[4]"
    Warning: No output dependent on input pin "D[5]"
    Warning: No output dependent on input pin "D[6]"
    Warning: No output dependent on input pin "D[7]"
Info: Implemented 29 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 13 output pins
    Info: Implemented 6 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 36 warnings
    Info: Processing ended: Sun Apr 05 22:05:18 2009
    Info: Elapsed time: 00:00:03