adc.tan.qmsg

adc0809用FPGA控制的采样非常好用的实例 自己看书后终结的

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register current_state.st2 current_state.st3 125.0 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 125.0 MHz between source register \"current_state.st2\" and destination register \"current_state.st3\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.300 ns + Longest register register " "Info: + Longest register to register delay is 2.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state.st2 1 REG LC6_A13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_A13; Fanout = 2; REG Node = 'current_state.st2'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "" { current_state.st2 } "NODE_NAME" } } { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 2.300 ns current_state.st3 2 REG LC1_A13 2 " "Info: 2: + IC(0.600 ns) + CELL(1.700 ns) = 2.300 ns; Loc. = LC1_A13; Fanout = 2; REG Node = 'current_state.st3'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "2.300 ns" { current_state.st2 current_state.st3 } "NODE_NAME" } } { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.700 ns ( 73.91 % ) " "Info: Total cell delay = 1.700 ns ( 73.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns ( 26.09 % ) " "Info: Total interconnect delay = 0.600 ns ( 26.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "2.300 ns" { current_state.st2 current_state.st3 } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "2.300 ns" { current_state.st2 current_state.st3 } { 0.000ns 0.600ns } { 0.000ns 1.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 6 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 6; CLK Node = 'CLK'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns current_state.st3 2 REG LC1_A13 2 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_A13; Fanout = 2; REG Node = 'current_state.st3'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "2.500 ns" { CLK current_state.st3 } "NODE_NAME" } } { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK current_state.st3 } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out current_state.st3 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 6 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 6; CLK Node = 'CLK'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns current_state.st2 2 REG LC6_A13 2 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC6_A13; Fanout = 2; REG Node = 'current_state.st2'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "2.500 ns" { CLK current_state.st2 } "NODE_NAME" } } { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK current_state.st2 } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out current_state.st2 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK current_state.st3 } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out current_state.st3 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK current_state.st2 } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out current_state.st2 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 43 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 43 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "2.300 ns" { current_state.st2 current_state.st3 } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "2.300 ns" { current_state.st2 current_state.st3 } { 0.000ns 0.600ns } { 0.000ns 1.700ns } } } { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK current_state.st3 } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out current_state.st3 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK current_state.st2 } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out current_state.st2 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "" { current_state.st3 } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "" { current_state.st3 } {  } {  } } } { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 43 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "current_state.st3 EOC CLK 2.900 ns register " "Info: tsu for register \"current_state.st3\" (data pin = \"EOC\", clock pin = \"CLK\") is 2.900 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.700 ns + Longest pin register " "Info: + Longest pin to register delay is 5.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns EOC 1 PIN PIN_84 2 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_84; Fanout = 2; PIN Node = 'EOC'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "" { EOC } "NODE_NAME" } } { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(1.200 ns) 5.700 ns current_state.st3 2 REG LC1_A13 2 " "Info: 2: + IC(1.700 ns) + CELL(1.200 ns) = 5.700 ns; Loc. = LC1_A13; Fanout = 2; REG Node = 'current_state.st3'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "2.900 ns" { EOC current_state.st3 } "NODE_NAME" } } { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 70.18 % ) " "Info: Total cell delay = 4.000 ns ( 70.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns ( 29.82 % ) " "Info: Total interconnect delay = 1.700 ns ( 29.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "5.700 ns" { EOC current_state.st3 } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "5.700 ns" { EOC EOC~out current_state.st3 } { 0.000ns 0.000ns 1.700ns } { 0.000ns 2.800ns 1.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 43 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.300 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 6 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 6; CLK Node = 'CLK'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns current_state.st3 2 REG LC1_A13 2 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_A13; Fanout = 2; REG Node = 'current_state.st3'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "2.500 ns" { CLK current_state.st3 } "NODE_NAME" } } { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK current_state.st3 } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out current_state.st3 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "5.700 ns" { EOC current_state.st3 } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "5.700 ns" { EOC EOC~out current_state.st3 } { 0.000ns 0.000ns 1.700ns } { 0.000ns 2.800ns 1.200ns } } } { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK current_state.st3 } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out current_state.st3 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK OE current_state.st3 16.800 ns register " "Info: tco from clock \"CLK\" to destination pin \"OE\" through register \"current_state.st3\" is 16.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.300 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 6 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 6; CLK Node = 'CLK'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns current_state.st3 2 REG LC1_A13 2 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_A13; Fanout = 2; REG Node = 'current_state.st3'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "2.500 ns" { CLK current_state.st3 } "NODE_NAME" } } { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK current_state.st3 } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out current_state.st3 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 43 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.400 ns + Longest register pin " "Info: + Longest register to pin delay is 10.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state.st3 1 REG LC1_A13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A13; Fanout = 2; REG Node = 'current_state.st3'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "" { current_state.st3 } "NODE_NAME" } } { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 2.900 ns OE~0 2 COMB LC3_A13 1 " "Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC3_A13; Fanout = 1; COMB Node = 'OE~0'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "2.900 ns" { current_state.st3 OE~0 } "NODE_NAME" } } { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(5.100 ns) 10.400 ns OE 3 PIN PIN_72 0 " "Info: 3: + IC(2.400 ns) + CELL(5.100 ns) = 10.400 ns; Loc. = PIN_72; Fanout = 0; PIN Node = 'OE'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "7.500 ns" { OE~0 OE } "NODE_NAME" } } { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.400 ns ( 71.15 % ) " "Info: Total cell delay = 7.400 ns ( 71.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 28.85 % ) " "Info: Total interconnect delay = 3.000 ns ( 28.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "10.400 ns" { current_state.st3 OE~0 OE } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "10.400 ns" { current_state.st3 OE~0 OE } { 0.000ns 0.600ns 2.400ns } { 0.000ns 2.300ns 5.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK current_state.st3 } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out current_state.st3 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "10.400 ns" { current_state.st3 OE~0 OE } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "10.400 ns" { current_state.st3 OE~0 OE } { 0.000ns 0.600ns 2.400ns } { 0.000ns 2.300ns 5.100ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "current_state.st3 EOC CLK 1.200 ns register " "Info: th for register \"current_state.st3\" (data pin = \"EOC\", clock pin = \"CLK\") is 1.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.300 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_43 6 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 6; CLK Node = 'CLK'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns current_state.st3 2 REG LC1_A13 2 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_A13; Fanout = 2; REG Node = 'current_state.st3'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "2.500 ns" { CLK current_state.st3 } "NODE_NAME" } } { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK current_state.st3 } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out current_state.st3 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 43 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.700 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns EOC 1 PIN PIN_84 2 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_84; Fanout = 2; PIN Node = 'EOC'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "" { EOC } "NODE_NAME" } } { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(1.200 ns) 5.700 ns current_state.st3 2 REG LC1_A13 2 " "Info: 2: + IC(1.700 ns) + CELL(1.200 ns) = 5.700 ns; Loc. = LC1_A13; Fanout = 2; REG Node = 'current_state.st3'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "2.900 ns" { EOC current_state.st3 } "NODE_NAME" } } { "ADC.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 70.18 % ) " "Info: Total cell delay = 4.000 ns ( 70.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns ( 29.82 % ) " "Info: Total interconnect delay = 1.700 ns ( 29.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "5.700 ns" { EOC current_state.st3 } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "5.700 ns" { EOC EOC~out current_state.st3 } { 0.000ns 0.000ns 1.700ns } { 0.000ns 2.800ns 1.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK current_state.st3 } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "5.300 ns" { CLK CLK~out current_state.st3 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "5.700 ns" { EOC current_state.st3 } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "5.700 ns" { EOC EOC~out current_state.st3 } { 0.000ns 0.000ns 1.700ns } { 0.000ns 2.800ns 1.200ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 05 22:05:30 2009 " "Info: Processing ended: Sun Apr 05 22:05:30 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}