📄 adc.fit.rpt
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; 81 ; GND* ; ;
; 82 ; GND_INT ; ;
; 83 ; D[4] ; TTL ;
; 84 ; EOC ; TTL ;
+-------+------------+--------------+
+-----------------------------------------------+
; Control Signals ;
+------+-------+---------+-------+--------------+
; Name ; Pin # ; Fan-Out ; Usage ; Global Usage ;
+------+-------+---------+-------+--------------+
; CLK ; 43 ; 6 ; Clock ; Pin ;
+------+-------+---------+-------+--------------+
+---------------------------------+
; Global & Other Fast Signals ;
+------+-------+---------+--------+
; Name ; Pin # ; Fan-Out ; Global ;
+------+-------+---------+--------+
; CLK ; 43 ; 6 ; yes ;
; EOC ; 84 ; 2 ; no ;
+------+-------+---------+--------+
+---------------------------------+
; Non-Global High Fan-Out Signals ;
+----------------------+----------+
; Name ; Fan-Out ;
+----------------------+----------+
; current_state.st1~15 ; 2 ;
; current_state.st0~8 ; 2 ;
; current_state.st2~7 ; 2 ;
; current_state.st3~14 ; 2 ;
; current_state.st4~15 ; 2 ;
; EOC ; 2 ;
; current_state.st1~16 ; 1 ;
; OE~1 ; 1 ;
+----------------------+----------+
+-------------------------------------------+
; LAB ;
+--------------------------+----------------+
; Number of Logic Elements ; Number of LABs ;
+--------------------------+----------------+
; 0 ; 71 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
+--------------------------+----------------+
+----------------------------------------------+
; Local Routing Interconnect ;
+-----------------------------+----------------+
; Local Routing Interconnects ; Number of LABs ;
+-----------------------------+----------------+
; 0 ; 71 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
+-----------------------------+----------------+
+---------------------------------------------+
; LAB External Interconnect ;
+----------------------------+----------------+
; LAB External Interconnects ; Number of LABs ;
+----------------------------+----------------+
; 0 ; 71 ;
; 1 ; 1 ;
+----------------------------+----------------+
+-----------------------------------------------------------------------------------------+
; Row Interconnect ;
+-------+--------------------+-----------------------------+------------------------------+
; Row ; Interconnect Used ; Left Half Interconnect Used ; Right Half Interconnect Used ;
+-------+--------------------+-----------------------------+------------------------------+
; A ; 2 / 96 ( 2 % ) ; 0 / 48 ( 0 % ) ; 1 / 48 ( 2 % ) ;
; B ; 0 / 96 ( 0 % ) ; 0 / 48 ( 0 % ) ; 0 / 48 ( 0 % ) ;
; C ; 0 / 96 ( 0 % ) ; 0 / 48 ( 0 % ) ; 0 / 48 ( 0 % ) ;
; Total ; 2 / 288 ( < 1 % ) ; 0 / 144 ( 0 % ) ; 1 / 144 ( < 1 % ) ;
+-------+--------------------+-----------------------------+------------------------------+
+---------------------------+
; LAB Column Interconnect ;
+-------+-------------------+
; Col. ; Interconnect Used ;
+-------+-------------------+
; 1 ; 0 / 24 ( 0 % ) ;
; 2 ; 0 / 24 ( 0 % ) ;
; 3 ; 0 / 24 ( 0 % ) ;
; 4 ; 0 / 24 ( 0 % ) ;
; 5 ; 0 / 24 ( 0 % ) ;
; 6 ; 0 / 24 ( 0 % ) ;
; 7 ; 0 / 24 ( 0 % ) ;
; 8 ; 0 / 24 ( 0 % ) ;
; 9 ; 0 / 24 ( 0 % ) ;
; 10 ; 0 / 24 ( 0 % ) ;
; 11 ; 0 / 24 ( 0 % ) ;
; 12 ; 0 / 24 ( 0 % ) ;
; 13 ; 0 / 24 ( 0 % ) ;
; 14 ; 0 / 24 ( 0 % ) ;
; 15 ; 0 / 24 ( 0 % ) ;
; 16 ; 0 / 24 ( 0 % ) ;
; 17 ; 0 / 24 ( 0 % ) ;
; 18 ; 0 / 24 ( 0 % ) ;
; 19 ; 0 / 24 ( 0 % ) ;
; 20 ; 0 / 24 ( 0 % ) ;
; 21 ; 0 / 24 ( 0 % ) ;
; 22 ; 0 / 24 ( 0 % ) ;
; 23 ; 0 / 24 ( 0 % ) ;
; 24 ; 0 / 24 ( 0 % ) ;
; Total ; 0 / 576 ( 0 % ) ;
+-------+-------------------+
+---------------------------+
; LAB Column Interconnect ;
+-------+-------------------+
; Col. ; Interconnect Used ;
+-------+-------------------+
; 1 ; 0 / 24 ( 0 % ) ;
; Total ; 0 / 24 ( 0 % ) ;
+-------+-------------------+
+-------------------------------------------------------+
; Fitter Resource Usage Summary ;
+-----------------------------------+-------------------+
; Resource ; Usage ;
+-----------------------------------+-------------------+
; Registers ; 6 / 576 ( 1 % ) ;
; Total LABs ; 0 / 72 ( 0 % ) ;
; Logic elements in carry chains ; 0 ;
; User inserted logic elements ; 0 ;
; I/O pins ; 23 / 59 ( 39 % ) ;
; -- Clock pins ; 1 ;
; -- Dedicated input pins ; 6 / 4 ( 150 % ) ;
; Global signals ; 1 ;
; EABs ; 0 / 3 ( 0 % ) ;
; Total memory bits ; 0 / 6,144 ( 0 % ) ;
; Total RAM block bits ; 0 / 6,144 ( 0 % ) ;
; Maximum fan-out node ; CLK ;
; Maximum fan-out ; 6 ;
; Highest non-global fan-out signal ; current_state.st1 ;
; Highest non-global fan-out ; 2 ;
; Total fan-out ; 20 ;
; Average fan-out ; 0.67 ;
+-----------------------------------+-------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |ADC ; 7 (7) ; 6 ; 0 ; 23 ; 1 (1) ; 1 (1) ; 5 (5) ; 0 (0) ; 0 (0) ; |ADC ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+--------------------------------+
; Delay Chain Summary ;
+-------+----------+-------------+
; Name ; Pin Type ; Pad to Core ;
+-------+----------+-------------+
; D[0] ; Input ; OFF ;
; D[1] ; Input ; OFF ;
; D[2] ; Input ; OFF ;
; D[3] ; Input ; OFF ;
; D[4] ; Input ; OFF ;
; D[5] ; Input ; OFF ;
; D[6] ; Input ; OFF ;
; D[7] ; Input ; OFF ;
; CLK ; Input ; OFF ;
; EOC ; Input ; OFF ;
; ALE ; Output ; OFF ;
; START ; Output ; OFF ;
; OE ; Output ; OFF ;
; ADDA ; Output ; OFF ;
; LOCK0 ; Output ; OFF ;
; Q[0] ; Output ; OFF ;
; Q[1] ; Output ; OFF ;
; Q[2] ; Output ; OFF ;
; Q[3] ; Output ; OFF ;
; Q[4] ; Output ; OFF ;
; Q[5] ; Output ; OFF ;
; Q[6] ; Output ; OFF ;
; Q[7] ; Output ; OFF ;
+-------+----------+-------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/quartus/chenggdechengxu/mokuai/ADCINT/ADC.pin.
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Sun Apr 05 22:05:21 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ADC -c ADC
Info: Selected device EPF10K10LC84-4 for design "ADC"
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Inserted 1 logic cells in first fitting attempt
Info: Started fitting attempt 1 on Sun Apr 05 2009 at 22:05:22
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Sun Apr 05 22:05:24 2009
Info: Elapsed time: 00:00:04
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