prev_cmp_key_board.tan.qmsg

自己写的键盘的扫描4乘4的键盘VHDL 很好用的

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WHDB_CLOCK_SETTING_NOT_FOUND" "CLK " "Warning: Can't find clock settings \"CLK\" in current project -- ignoring clock settings" {  } {  } 0 0 "Can't find clock settings \"%1!s!\" in current project -- ignoring clock settings" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register LINE\[2\]~reg0 register KEYVAL\[0\] 36.63 MHz 27.3 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 36.63 MHz between source register \"LINE\[2\]~reg0\" and destination register \"KEYVAL\[0\]\" (period= 27.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "23.700 ns + Longest register register " "Info: + Longest register to register delay is 23.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LINE\[2\]~reg0 1 REG LC4_B8 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B8; Fanout = 16; REG Node = 'LINE\[2\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { LINE[2]~reg0 } "NODE_NAME" } } { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(2.300 ns) 5.900 ns Mux3~475 2 COMB LC2_A11 1 " "Info: 2: + IC(3.600 ns) + CELL(2.300 ns) = 5.900 ns; Loc. = LC2_A11; Fanout = 1; COMB Node = 'Mux3~475'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { LINE[2]~reg0 Mux3~475 } "NODE_NAME" } } { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.800 ns) 9.900 ns Mux3~476 3 COMB LC4_A6 1 " "Info: 3: + IC(2.200 ns) + CELL(1.800 ns) = 9.900 ns; Loc. = LC4_A6; Fanout = 1; COMB Node = 'Mux3~476'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { Mux3~475 Mux3~476 } "NODE_NAME" } } { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(2.300 ns) 14.500 ns Mux3~478 4 COMB LC6_A11 1 " "Info: 4: + IC(2.300 ns) + CELL(2.300 ns) = 14.500 ns; Loc. = LC6_A11; Fanout = 1; COMB Node = 'Mux3~478'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { Mux3~476 Mux3~478 } "NODE_NAME" } } { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 17.400 ns Mux3~481 5 COMB LC1_A11 1 " "Info: 5: + IC(0.600 ns) + CELL(2.300 ns) = 17.400 ns; Loc. = LC1_A11; Fanout = 1; COMB Node = 'Mux3~481'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { Mux3~478 Mux3~481 } "NODE_NAME" } } { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 21.900 ns Mux3~482 6 COMB LC3_A5 1 " "Info: 6: + IC(2.200 ns) + CELL(2.300 ns) = 21.900 ns; Loc. = LC3_A5; Fanout = 1; COMB Node = 'Mux3~482'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { Mux3~481 Mux3~482 } "NODE_NAME" } } { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 23.700 ns KEYVAL\[0\] 7 REG LC8_A5 9 " "Info: 7: + IC(0.600 ns) + CELL(1.200 ns) = 23.700 ns; Loc. = LC8_A5; Fanout = 9; REG Node = 'KEYVAL\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.800 ns" { Mux3~482 KEYVAL[0] } "NODE_NAME" } } { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.200 ns ( 51.48 % ) " "Info: Total cell delay = 12.200 ns ( 51.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.500 ns ( 48.52 % ) " "Info: Total interconnect delay = 11.500 ns ( 48.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "23.700 ns" { LINE[2]~reg0 Mux3~475 Mux3~476 Mux3~478 Mux3~481 Mux3~482 KEYVAL[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "23.700 ns" { LINE[2]~reg0 {} Mux3~475 {} Mux3~476 {} Mux3~478 {} Mux3~481 {} Mux3~482 {} KEYVAL[0] {} } { 0.000ns 3.600ns 2.200ns 2.300ns 0.600ns 2.200ns 0.600ns } { 0.000ns 2.300ns 1.800ns 2.300ns 2.300ns 2.300ns 1.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_1 14 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_1; Fanout = 14; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns KEYVAL\[0\] 2 REG LC8_A5 9 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_A5; Fanout = 9; REG Node = 'KEYVAL\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { CLK KEYVAL[0] } "NODE_NAME" } } { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK KEYVAL[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { CLK {} CLK~out {} KEYVAL[0] {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_1 14 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_1; Fanout = 14; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns LINE\[2\]~reg0 2 REG LC4_B8 16 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_B8; Fanout = 16; REG Node = 'LINE\[2\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { CLK LINE[2]~reg0 } "NODE_NAME" } } { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK LINE[2]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { CLK {} CLK~out {} LINE[2]~reg0 {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK KEYVAL[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { CLK {} CLK~out {} KEYVAL[0] {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK LINE[2]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { CLK {} CLK~out {} LINE[2]~reg0 {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 20 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "23.700 ns" { LINE[2]~reg0 Mux3~475 Mux3~476 Mux3~478 Mux3~481 Mux3~482 KEYVAL[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "23.700 ns" { LINE[2]~reg0 {} Mux3~475 {} Mux3~476 {} Mux3~478 {} Mux3~481 {} Mux3~482 {} KEYVAL[0] {} } { 0.000ns 3.600ns 2.200ns 2.300ns 0.600ns 2.200ns 0.600ns } { 0.000ns 2.300ns 1.800ns 2.300ns 2.300ns 2.300ns 1.200ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK KEYVAL[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { CLK {} CLK~out {} KEYVAL[0] {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK LINE[2]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { CLK {} CLK~out {} LINE[2]~reg0 {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "KEYVAL\[0\] COLUMN\[1\] CLK 25.500 ns register " "Info: tsu for register \"KEYVAL\[0\]\" (data pin = \"COLUMN\[1\]\", clock pin = \"CLK\") is 25.500 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "28.300 ns + Longest pin register " "Info: + Longest pin to register delay is 28.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns COLUMN\[1\] 1 PIN PIN_48 15 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_48; Fanout = 15; PIN Node = 'COLUMN\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { COLUMN[1] } "NODE_NAME" } } { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.700 ns) + CELL(2.300 ns) 10.500 ns Mux3~475 2 COMB LC2_A11 1 " "Info: 2: + IC(4.700 ns) + CELL(2.300 ns) = 10.500 ns; Loc. = LC2_A11; Fanout = 1; COMB Node = 'Mux3~475'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { COLUMN[1] Mux3~475 } "NODE_NAME" } } { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.800 ns) 14.500 ns Mux3~476 3 COMB LC4_A6 1 " "Info: 3: + IC(2.200 ns) + CELL(1.800 ns) = 14.500 ns; Loc. = LC4_A6; Fanout = 1; COMB Node = 'Mux3~476'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { Mux3~475 Mux3~476 } "NODE_NAME" } } { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(2.300 ns) 19.100 ns Mux3~478 4 COMB LC6_A11 1 " "Info: 4: + IC(2.300 ns) + CELL(2.300 ns) = 19.100 ns; Loc. = LC6_A11; Fanout = 1; COMB Node = 'Mux3~478'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { Mux3~476 Mux3~478 } "NODE_NAME" } } { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 22.000 ns Mux3~481 5 COMB LC1_A11 1 " "Info: 5: + IC(0.600 ns) + CELL(2.300 ns) = 22.000 ns; Loc. = LC1_A11; Fanout = 1; COMB Node = 'Mux3~481'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { Mux3~478 Mux3~481 } "NODE_NAME" } } { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 26.500 ns Mux3~482 6 COMB LC3_A5 1 " "Info: 6: + IC(2.200 ns) + CELL(2.300 ns) = 26.500 ns; Loc. = LC3_A5; Fanout = 1; COMB Node = 'Mux3~482'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { Mux3~481 Mux3~482 } "NODE_NAME" } } { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 28.300 ns KEYVAL\[0\] 7 REG LC8_A5 9 " "Info: 7: + IC(0.600 ns) + CELL(1.200 ns) = 28.300 ns; Loc. = LC8_A5; Fanout = 9; REG Node = 'KEYVAL\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.800 ns" { Mux3~482 KEYVAL[0] } "NODE_NAME" } } { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "15.700 ns ( 55.48 % ) " "Info: Total cell delay = 15.700 ns ( 55.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.600 ns ( 44.52 % ) " "Info: Total interconnect delay = 12.600 ns ( 44.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "28.300 ns" { COLUMN[1] Mux3~475 Mux3~476 Mux3~478 Mux3~481 Mux3~482 KEYVAL[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "28.300 ns" { COLUMN[1] {} COLUMN[1]~out {} Mux3~475 {} Mux3~476 {} Mux3~478 {} Mux3~481 {} Mux3~482 {} KEYVAL[0] {} } { 0.000ns 0.000ns 4.700ns 2.200ns 2.300ns 0.600ns 2.200ns 0.600ns } { 0.000ns 3.500ns 2.300ns 1.800ns 2.300ns 2.300ns 2.300ns 1.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.300 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK 1 CLK PIN_1 14 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_1; Fanout = 14; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns KEYVAL\[0\] 2 REG LC8_A5 9 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_A5; Fanout = 9; REG Node = 'KEYVAL\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { CLK KEYVAL[0] } "NODE_NAME" } } { "KEY_BOARD.vhd" "" { Text "E:/quartus/chenggdechengxu/mokuai/key/KEY_BOARD.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK KEYVAL[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { CLK {} CLK~out {} KEYVAL[0] {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "28.300 ns" { COLUMN[1] Mux3~475 Mux3~476 Mux3~478 Mux3~481 Mux3~482 KEYVAL[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "28.300 ns" { COLUMN[1] {} COLUMN[1]~out {} Mux3~475 {} Mux3~476 {} Mux3~478 {} Mux3~481 {} Mux3~482 {} KEYVAL[0] {} } { 0.000ns 0.000ns 4.700ns 2.200ns 2.300ns 0.600ns 2.200ns 0.600ns } { 0.000ns 3.500ns 2.300ns 1.800ns 2.300ns 2.300ns 2.300ns 1.200ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { CLK KEYVAL[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { CLK {} CLK~out {} KEYVAL[0] {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}