key_board.tan.rpt

自己写的键盘的扫描4乘4的键盘VHDL 很好用的

; N/A           ; None        ; -8.300 ns  ; COLUMN[2] ; HIT_FLAG          ; CLK      ;
; N/A           ; None        ; -8.300 ns  ; COLUMN[2] ; FLAG_OUT~reg0     ; CLK      ;
; N/A           ; None        ; -9.900 ns  ; COLUMN[0] ; KEYVAL[0]         ; CLK      ;
; N/A           ; None        ; -10.000 ns ; COLUMN[3] ; KEY_VALUE[0]~reg0 ; CLK      ;
; N/A           ; None        ; -10.000 ns ; COLUMN[3] ; KEY_VALUE[1]~reg0 ; CLK      ;
; N/A           ; None        ; -10.000 ns ; COLUMN[3] ; KEY_VALUE[2]~reg0 ; CLK      ;
; N/A           ; None        ; -10.000 ns ; COLUMN[3] ; KEY_VALUE[3]~reg0 ; CLK      ;
; N/A           ; None        ; -10.200 ns ; COLUMN[1] ; KEY_VALUE[0]~reg0 ; CLK      ;
; N/A           ; None        ; -10.200 ns ; COLUMN[1] ; KEY_VALUE[1]~reg0 ; CLK      ;
; N/A           ; None        ; -10.200 ns ; COLUMN[1] ; KEYVAL[1]         ; CLK      ;
; N/A           ; None        ; -10.200 ns ; COLUMN[1] ; KEY_VALUE[2]~reg0 ; CLK      ;
; N/A           ; None        ; -10.200 ns ; COLUMN[1] ; KEY_VALUE[3]~reg0 ; CLK      ;
; N/A           ; None        ; -10.600 ns ; COLUMN[0] ; KEY_VALUE[0]~reg0 ; CLK      ;
; N/A           ; None        ; -10.600 ns ; COLUMN[0] ; KEY_VALUE[1]~reg0 ; CLK      ;
; N/A           ; None        ; -10.600 ns ; COLUMN[0] ; KEY_VALUE[2]~reg0 ; CLK      ;
; N/A           ; None        ; -10.600 ns ; COLUMN[0] ; KEY_VALUE[3]~reg0 ; CLK      ;
; N/A           ; None        ; -10.700 ns ; COLUMN[2] ; KEY_VALUE[0]~reg0 ; CLK      ;
; N/A           ; None        ; -10.700 ns ; COLUMN[2] ; KEY_VALUE[1]~reg0 ; CLK      ;
; N/A           ; None        ; -10.700 ns ; COLUMN[2] ; KEY_VALUE[2]~reg0 ; CLK      ;
; N/A           ; None        ; -10.700 ns ; COLUMN[2] ; KEY_VALUE[3]~reg0 ; CLK      ;
; N/A           ; None        ; -10.700 ns ; COLUMN[0] ; KEYVAL[1]         ; CLK      ;
; N/A           ; None        ; -10.800 ns ; COLUMN[2] ; KEYVAL[1]         ; CLK      ;
; N/A           ; None        ; -11.600 ns ; COLUMN[1] ; KEYVAL[0]         ; CLK      ;
; N/A           ; None        ; -12.100 ns ; COLUMN[2] ; KEYVAL[0]         ; CLK      ;
+---------------+-------------+------------+-----------+-------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Tue Apr 07 15:58:22 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off KEY_BOARD -c KEY_BOARD
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Can't find clock settings "CLK" in current project -- ignoring clock settings
Info: Clock "CLK" has Internal fmax of 36.63 MHz between source register "LINE[2]~reg0" and destination register "KEYVAL[0]" (period= 27.3 ns)
    Info: + Longest register to register delay is 23.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B8; Fanout = 16; REG Node = 'LINE[2]~reg0'
        Info: 2: + IC(3.600 ns) + CELL(2.300 ns) = 5.900 ns; Loc. = LC2_A11; Fanout = 1; COMB Node = 'Mux3~475'
        Info: 3: + IC(2.200 ns) + CELL(1.800 ns) = 9.900 ns; Loc. = LC4_A6; Fanout = 1; COMB Node = 'Mux3~476'
        Info: 4: + IC(2.300 ns) + CELL(2.300 ns) = 14.500 ns; Loc. = LC6_A11; Fanout = 1; COMB Node = 'Mux3~478'
        Info: 5: + IC(0.600 ns) + CELL(2.300 ns) = 17.400 ns; Loc. = LC1_A11; Fanout = 1; COMB Node = 'Mux3~481'
        Info: 6: + IC(2.200 ns) + CELL(2.300 ns) = 21.900 ns; Loc. = LC3_A5; Fanout = 1; COMB Node = 'Mux3~482'
        Info: 7: + IC(0.600 ns) + CELL(1.200 ns) = 23.700 ns; Loc. = LC8_A5; Fanout = 9; REG Node = 'KEYVAL[0]'
        Info: Total cell delay = 12.200 ns ( 51.48 % )
        Info: Total interconnect delay = 11.500 ns ( 48.52 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 5.300 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_1; Fanout = 14; CLK Node = 'CLK'
            Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_A5; Fanout = 9; REG Node = 'KEYVAL[0]'
            Info: Total cell delay = 2.800 ns ( 52.83 % )
            Info: Total interconnect delay = 2.500 ns ( 47.17 % )
        Info: - Longest clock path from clock "CLK" to source register is 5.300 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_1; Fanout = 14; CLK Node = 'CLK'
            Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_B8; Fanout = 16; REG Node = 'LINE[2]~reg0'
            Info: Total cell delay = 2.800 ns ( 52.83 % )
            Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 2.500 ns
Info: tsu for register "KEYVAL[0]" (data pin = "COLUMN[1]", clock pin = "CLK") is 25.500 ns
    Info: + Longest pin to register delay is 28.300 ns
        Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_48; Fanout = 15; PIN Node = 'COLUMN[1]'
        Info: 2: + IC(4.700 ns) + CELL(2.300 ns) = 10.500 ns; Loc. = LC2_A11; Fanout = 1; COMB Node = 'Mux3~475'
        Info: 3: + IC(2.200 ns) + CELL(1.800 ns) = 14.500 ns; Loc. = LC4_A6; Fanout = 1; COMB Node = 'Mux3~476'
        Info: 4: + IC(2.300 ns) + CELL(2.300 ns) = 19.100 ns; Loc. = LC6_A11; Fanout = 1; COMB Node = 'Mux3~478'
        Info: 5: + IC(0.600 ns) + CELL(2.300 ns) = 22.000 ns; Loc. = LC1_A11; Fanout = 1; COMB Node = 'Mux3~481'
        Info: 6: + IC(2.200 ns) + CELL(2.300 ns) = 26.500 ns; Loc. = LC3_A5; Fanout = 1; COMB Node = 'Mux3~482'
        Info: 7: + IC(0.600 ns) + CELL(1.200 ns) = 28.300 ns; Loc. = LC8_A5; Fanout = 9; REG Node = 'KEYVAL[0]'
        Info: Total cell delay = 15.700 ns ( 55.48 % )
        Info: Total interconnect delay = 12.600 ns ( 44.52 % )
    Info: + Micro setup delay of destination is 2.500 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_1; Fanout = 14; CLK Node = 'CLK'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_A5; Fanout = 9; REG Node = 'KEYVAL[0]'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
Info: tco from clock "CLK" to destination pin "LINE[3]" through register "LINE[3]~reg0" is 14.100 ns
    Info: + Longest clock path from clock "CLK" to source register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_1; Fanout = 14; CLK Node = 'CLK'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC6_A9; Fanout = 12; REG Node = 'LINE[3]~reg0'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 7.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_A9; Fanout = 12; REG Node = 'LINE[3]~reg0'
        Info: 2: + IC(2.600 ns) + CELL(5.100 ns) = 7.700 ns; Loc. = PIN_24; Fanout = 0; PIN Node = 'LINE[3]'
        Info: Total cell delay = 5.100 ns ( 66.23 % )
        Info: Total interconnect delay = 2.600 ns ( 33.77 % )
Info: th for register "KEYVAL[1]" (data pin = "COLUMN[3]", clock pin = "CLK") is -2.300 ns
    Info: + Longest clock path from clock "CLK" to destination register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_1; Fanout = 14; CLK Node = 'CLK'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_A5; Fanout = 7; REG Node = 'KEYVAL[1]'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro hold delay of destination is 1.600 ns
    Info: - Shortest pin to register delay is 9.200 ns
        Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_50; Fanout = 10; PIN Node = 'COLUMN[3]'
        Info: 2: + IC(4.500 ns) + CELL(1.200 ns) = 9.200 ns; Loc. = LC1_A5; Fanout = 7; REG Node = 'KEYVAL[1]'
        Info: Total cell delay = 4.700 ns ( 51.09 % )
        Info: Total interconnect delay = 4.500 ns ( 48.91 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 110 megabytes of memory during processing
    Info: Processing ended: Tue Apr 07 15:58:24 2009
    Info: Elapsed time: 00:00:02