vga_ctrl.v

基于NIOS II 的DE1开发板的VGA 控制器VGA控制模块主要控制VGA模块的开始和其运行的状态

module	VGA_Ctrl	(	//	Host Side
						
						oCurrent_X,
						oCurrent_Y,
						
						oRequest,
					    oVGA_VS,
						//	Control Signal
						ienable_y,
						ienable3,
						iCLK,
						iRST_N	);
//	Host Side

output		[9:0]	oCurrent_X;
output		[10:0]	oCurrent_Y;
output				oRequest;

output              oVGA_VS;
//	Control Signal
input               ienable3;
input               ienable_y;
input				iCLK;
input				iRST_N;	
//	Internal Registers
////////////////////////////////////////////////////////////
reg   oVGA_HS;
reg   oVGA_VS;
reg [10:0]H_Cont;
reg [10:0]V_Cont;
//	Horizontal	Parameter

parameter	H_TOTAL	=	640;

parameter	V_TOTAL	=	480;
////////////////////////////////////////////////////////////

assign	oRequest	=	 ((H_Cont>=0 && H_Cont<H_TOTAL)	&&
						  (V_Cont>=0 && V_Cont<V_TOTAL) && ienable_y && ienable3) ;
assign	oCurrent_X	=	H_Cont;
assign	oCurrent_Y	=	ienable_y	?	V_Cont	:	11'h0	;

//	Horizontal Generator: Refer to the pixel clock
always@( posedge iCLK or negedge iRST_N )
begin
	if(!iRST_N)
	begin
		H_Cont		<=	0;
		oVGA_HS     <= 1'b0;
	end
	else
	begin
		if( (H_Cont<H_TOTAL) && ienable3 )  
		H_Cont	<=	H_Cont+1'b1;
		else
		H_Cont	<=	H_Cont;
		//	Horizontal Sync
		if(H_Cont==640)	//	Sync pulse end
		  begin
		   oVGA_HS	<=	1'b1;
		   H_Cont   <=  1'b0;
		  end
		else
		   oVGA_HS  <=  1'b0;
	end
end

//	Vertical Generator: Refer to the horizontal sync
always@(posedge oVGA_HS or negedge iRST_N )
begin
	if(!iRST_N)
	begin
		V_Cont		<=	0;
		
	end
	else
	begin
		if(V_Cont<V_TOTAL) 
		V_Cont	<=	V_Cont+1'b1;
		else
		V_Cont	<=	0;
		//	Vertical Sync
		if(V_Cont == 480 )
		   oVGA_VS <= 1;
		else
		   oVGA_VS <= 0;
		
	end
end

endmodule