yuv_rgb.v

来自「完成ITUR656标准的视频流数据向RGB格式的转换。」· Verilog 代码 · 共 47 行

module  yuv_rgb (clock,clocken,reset,y,cr,cb,r,g,b);
input clock,clocken,reset;
input  [7:0] y,cr,cb;
output reg [7:0] r,g,b;
reg   [7:0] y1,cr1,cb1;
 
 wire [7:0] r_sig;  
wire [7:0] g_sig;  
wire [7:0] b_sig; 
 
always @(posedge clock or posedge reset) 
begin : In_Reg 
if (reset) 
begin 
y1<= 0; 
cr1 <= 0; 
cb1<= 0; 
end 
else if (clocken) 
begin 
y1 <= y ;  
cr1 <= cr ;  
cb1<= cb;  
end  
end  

// Output registers (should be pushed into IOBs) 
always @(posedge clock or posedge reset) 
begin : Out_Reg 
if (reset) 
begin 
r <= 0; 
g<= 0; 
b <= 0; 
end 
else if (clocken) 
begin 
r <= r_sig ;  
g <= g_sig ;  
b <= b_sig ;  
end  
end  

 csc  uut(.clock(clock),.clocken(clocken),.reset(reset),.y(y),.cr(cr),.cb(cb),.r(r_sig),.g(g_sig),.b(b_sig));
 

 endmodule