cordic_tb.vhd

cordic implementation in vhdl&c

--Template testbench generated by genTemplateTb.pl for cordic
LIBRARY IEEE ;
   USE IEEE.std_logic_1164.ALL ;
   USE WORK.fun_pkg.ALL ;
   USE IEEE.std_logic_signed.ALL ;
  use work.fun_pkg.all;

ENTITY cordic_tb is 
GENERIC(wi : integer := 25);
END cordic_tb ;

ARCHITECTURE tb of cordic_tb is 

signal clk : std_logic  ;
signal rstn : std_logic  ;
signal angle : std_logic_vector ( wi-1 downto 0 )  ;
signal angle_valid : std_logic  ;
signal sinout : std_logic_vector ( wi-1 downto 0 )  ;
signal cosout : std_logic_vector ( wi-1 downto 0 )  ;
signal ready : std_logic     ;

--TB SIGNALS
signal tb_clk     : std_logic := '0' ;
signal tb_rstn    : std_logic := '0' ;
signal tb_counter : integer   := 0 ;
signal tb_counter_vec : std_logic_vector(31 downto 0) := (others => '0') ;
signal tb_lfsr : std_logic_vector(31 downto 0) := (others => '0') ;
  --tb_lfsr is a 32 bit pseudo random generator, and can be used 
  --as a source of random data
  --Any bit of it can be used as a source of randomised serial data

-- synopsys translate_off
constant tb_clk_period : time := 5 ns;
-- synopsys translate_on

component cordic
PORT ( 
  clk : in std_logic  ;
  rstn : in std_logic  ;
  angle : in std_logic_vector ( wi-1 downto 0 )  ;
  angle_valid : in std_logic  ;
  sinout : out std_logic_vector ( wi-1 downto 0 )  ;
  cosout : out std_logic_vector ( wi-1 downto 0 )  ;
  ready : out std_logic     
);
END COMPONENT ;

BEGIN
cordic_u1 : cordic
PORT MAP( 
  clk => tb_clk ,
  rstn => tb_rstn ,
  angle => angle ,
  angle_valid => angle_valid ,
  sinout => sinout ,
  cosout => cosout ,
  ready => ready 
);

-- synopsys translate_off
tb_clk <= not(tb_clk) after tb_clk_period ;
tb_rstn <= '1' after tb_clk_period * 5 + 1 ns;
-- synopsys translate_on

tb_counter_p : PROCESS (tb_clk)
begin
if(tb_rstn = '0') then
  tb_counter <= 0;
  tb_counter_vec <= (others => '0');
  tb_lfsr <= (others => '0');
elsif(rising_edge(tb_clk)) then
  tb_counter <= tb_counter + 1;
  tb_counter_vec <= incr_vec(tb_counter_vec,'1');
  tb_lfsr(31) <= not(tb_lfsr(31) xor tb_lfsr(21) xor tb_lfsr(1) xor tb_lfsr(0));
  tb_lfsr(30 downto 0) <= tb_lfsr(31 downto 1);
end if;
end process tb_counter_p;

--angle_valid <= tb_counter_vec(5);
--angle <= "010101111111111111111111";
--Angle is first divided by 128, then converted into 24 bit fixed point number

--assign_angle_p : process(tb_clk)
--begin
--  if(rising_edge(tb_clk)) then
--    if(rstn = '0') then
--      angle <= (others => '0');
--    elsif(tb
--    end if;
--  end if;
--end process assign_angle_p;

angle_valid <=  '0' after 20 ns, 
                '1' after 200 ns,
                '0' after 800 ns,
                '1' after 1100 ns,
                '0' after 1800 ns,
                '1' after 2100 ns,
                '0' after 2800 ns,
                '1' after 3100 ns,
                '0' after 3800 ns,
                '1' after 4100 ns,
                '0' after 4800 ns,
                '1' after 5100 ns,
                '0' after 5800 ns,
                '1' after 6100 ns,
                '0' after 6800 ns,
                '1' after 7100 ns,
                '0' after 7800 ns,
                '1' after 8100 ns,
                '0' after 8800 ns,
                '1' after 9100 ns,
                '0' after 9800 ns,
                '1' after 10100 ns,
                '0' after 10800 ns,
                '1' after 11100 ns,
                '0' after 11800 ns;

angle <= "0001011000000000000000000" after 100 ns, --22 Degrees
"0001111000000000000000000" after 1 us, --30 Degrees
"0010100010000000000000000" after 2 us, --40.5 Degrees
"0011110011100110011001100" after 3 us, --60.9 Degrees
"0100011000110000101000111" after 4 us, --70.19 Degrees
"0101010011111111111111111" after 5 us, --85 Degrees
"0101101000000000000000000" after 6 us, --90 Degrees
"0000000000000000000000000" after 7 us, --0 Degrees
"0101100011111111111111111" after 8 us, --89 Degrees
"0000000100000000000000000" after 9 us; --1 Degrees

END TB;