fun_pkg.vhdl

cordic implementation in vhdl&c

        RETURN Z; 
        END all_ones; -- end function

FUNCTION all_zeros(s1:std_logic_vector) return std_logic is 
                  --this function tells if all bits of a vector are '0'
                  --return value Z if '1', then vector has all 0 bits
        --VARIABLE V : std_logic_vector(s1'high downto s1'low) ; 
        VARIABLE Z : std_logic; 
        BEGIN 
        Z := '0'; 
        FOR i IN (s1'low) to s1'high LOOP 
            Z := Z OR s1(i); 
        END LOOP; 
        RETURN not(Z); 
        END all_zeros; -- end function

FUNCTION mux1(a0:std_logic;a1:std_logic;sel:std_logic) return std_logic is 
        --a 1 bit mux, handy to be used combinational assignments.
        --output = a0, if sel = 0, 
        --output = a1,if sel = 1.
        VARIABLE Z: std_logic;
        BEGIN 
          IF(sel = '0') THEN
            Z := a0;
          ELSE
            Z := a1;
          END IF;
        RETURN Z; 
        END mux1; -- end function

FUNCTION mux_vec(a0:std_logic_vector;a1:std_logic_vector;sel:std_logic) 
return std_logic_vector is 
        --a vectored mux, handy to be used combinational assignments.
        --output = a0, if sel = 0, 
        --output = a1,if sel = 1.
        VARIABLE Z: std_logic_vector(a0'high downto a0'low);
        BEGIN 
          IF(sel = '0') THEN
            Z := a0;
          ELSE
            Z := a1;
          END IF;
        RETURN Z; 
        END mux_vec; -- end function

FUNCTION if_eq(s1:std_logic_vector;s2:std_logic_vector) return std_logic is 
        --this function returns a value of '1' if the passed
        --input1 vector is equal to the input2 value
        --Usage:
        -- mybit = if_eq(sig1,const1);
        -- where sig1 and const1 are equal in widths
        -- This function works only with 'constant' types 
        -- The function must be passed a 'constant' type
        -- for its variable 'const1', otherwise potential problems may
        -- arise
        VARIABLE V : std_logic_vector(s1'high downto s1'low) ; 
        VARIABLE Z : std_logic; 
        BEGIN 
        FOR i IN (s1'high) downto (s1'low) LOOP 
          V(i) := s1(i) XOR s2(i); 
        END LOOP; 
        Z := all_zeros(V);
        RETURN Z; 
        END if_eq; -- end function


FUNCTION inv_if_one(s1:std_logic_vector;en:std_logic) return std_logic_vector is 
                  --this function inverts all the bits of a vector if
                  --'en' is '1'.
        VARIABLE Z : std_logic_vector(s1'high downto s1'low); 
        BEGIN 
        FOR i IN (s1'low) to s1'high LOOP 
            Z(i) := en XOR s1(i); 
        END LOOP; 
        RETURN Z; 
        END inv_if_one; -- end function

FUNCTION inv(s1:std_logic_vector) return std_logic_vector is 
                  --this function inverts all the bits of input vector
        VARIABLE Z : std_logic_vector(s1'high downto s1'low); 
        BEGIN 
        FOR i IN (s1'low) to s1'high LOOP 
            Z(i) := NOT(s1(i)); 
        END LOOP; 
        RETURN Z; 
        END inv; -- end function

FUNCTION twos_comp(s1:std_logic_vector) return std_logic_vector is 
        VARIABLE Z : std_logic_vector(s1'high downto s1'low); 
        --Finds twos compliment of an std_logic_vector type.
        --will do nothing to +ive numbers.(which have their msb='0'
        BEGIN
          Z := inv_if_one(s1,s1(s1'high));
          Z := incr_vec(Z,s1(s1'high));
        RETURN Z;
        END twos_comp; -- end function
FUNCTION tc(s1:std_logic_vector) return std_logic_vector is 
        VARIABLE Z : std_logic_vector(s1'high downto s1'low); 
        --Finds twos compliment of an std_logic_vector type.
        --No matter input is -ive or +ive, it will always return
        --output = NOT(input) + 1;
        BEGIN
          Z := inv(s1);
          Z := incr_vec(Z,'1');
        RETURN Z;
        END tc; -- end function
FUNCTION myabs(s1:std_logic_vector) return std_logic_vector is 
          --this function returns an absolute value of a vector
          --This is same as the function 'twos_comp' above
        VARIABLE V : std_logic_vector(s1'high downto s1'low) ; 
        BEGIN 
        for i in V'low to V'high loop 
          V(i) := s1(i) XOR s1(s1'high); 
        end loop; 
        V := incr_vec(V,s1(s1'high));
        return V; 
        end myabs; -- end function 

FUNCTION NextGray(G1:std_logic_vector) return std_logic_vector is
    VARIABLE G2 : std_logic_vector(G1'high downto G1'low) ;
    VARIABLE B1 : std_logic_vector(G1'high downto G1'low) ;
    VARIABLE tb : std_logic_vector(G1'high downto G1'low);
    BEGIN
    if(G1'length <= 2) then
    assert false
      report "NextGray: Min Vector Length in Function is 3" severity error;
    end if;

    if(all_zeros(not(G1(G1'high)) & G1(G1'high-1 downto G1'low)) = '1') then
      G2 := (others => '0');
      return G2;
    end if;
    B1 := gray2bin(G1);
    tb(G1'low) := not(B1(B1'low));

    tb(G1'low + 1) := G1(G1'low) and B1(B1'low);

    for i in (G1'low + 2) to G1'high loop
      tb(i) := all_zeros( not(G1(i-1)) & G1(i-2 downto G1'low) & not(B1(B1'low)) );
    end loop;

    G2:=G1;
    for i in G1'low to G1'high loop
     if(tb(i) = '1') then
       G2(i) := not(G2(i));
     end if;
    end loop;


    return G2;
    end NextGray; -- end function

  FUNCTION sshr(s1:std_logic_vector) return std_logic_vector is
    variable r : std_logic_vector(s1'high downto s1'low);
  begin
    r(r'high) := s1(s1'high);    
    r(r'high -1 downto 0) := s1(s1'high downto 1);    
    return r;
  end sshr; 

  FUNCTION csshr(s1:std_logic_vector;s2:std_logic) return std_logic_vector is
    variable r : std_logic_vector(s1'high downto s1'low);
  begin
    if(s2 = '1') then
      r(r'high) := s1(s1'high);    
      r(r'high -1 downto 0) := s1(s1'high downto 1);    
    else
      r := s1;
    end if;
    return r;
  end csshr; 

  FUNCTION zshr(s1:std_logic_vector) return std_logic_vector is
    variable r : std_logic_vector(s1'high downto s1'low);
  begin
    r(r'high) := '0';
    r(r'high -1 downto 0) := s1(s1'high downto 1);    
    return r;
  end zshr; 

  FUNCTION czshr(s1:std_logic_vector;s2:std_logic) return std_logic_vector is
    variable r : std_logic_vector(s1'high downto s1'low);
  begin
    if(s2 = '1') then
      r(r'high) := '0';
      r(r'high -1 downto 0) := s1(s1'high downto 1);    
    else
      r := s1;
    end if;
    return r;
  end czshr; 

  FUNCTION zshrn(s1:std_logic_vector;n:integer) return std_logic_vector is
    variable r : std_logic_vector(s1'high downto s1'low);
  begin
    --pragma translate_off
    --pragma coverage_off
    if(n < 0) then
    assert false
      report "zshrn: shift index is negative,can't rotate" severity error;
    end if;
    --pragma translate_on
    --pragma coverage_on
    r := s1;
    if(n = 0) then
      return r;
    end if;
    r(r'high downto r'high-(n-1)) := (others => '0');
    r(r'high -n downto 0) := s1(s1'high downto n);
    return r;
  end zshrn; 

  FUNCTION sshrn(s1:std_logic_vector;nn:integer) return std_logic_vector is
    variable rr : std_logic_vector(s1'high downto s1'low);
  begin
    --pragma translate_off
    --pragma coverage_off
    if(nn < 0) then
    assert false
      report "sshrn: shift index is negative,can't rotate" severity error;
    end if;
    --pragma translate_on
    --pragma coverage_on
    if(nn = 0) then
      rr := s1;
    else
      rr := (others => s1(s1'high));
      for ii in s1'high downto 0 loop
        rr(ii-nn) := s1(ii);
        if(ii = nn) then
          exit;
        end if;
      end loop;
    end if;
    return rr;
  end sshrn; 


  FUNCTION shl(s1:std_logic_vector) return std_logic_vector is
    variable r : std_logic_vector(s1'high downto s1'low);
  begin
    r(r'low) := '0';
    r(r'high downto 1) := s1(s1'high-1 downto 0);    
    return r;
  end shl; 

--Function Declaration Section Ends
END fun_pkg;