fun_pkg.vhdl

cordic implementation in vhdl&c

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--Generated by Utility gen_entity.pl by Aviral Mittal
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--Following is a pkg file, defining some commonly used vhdl functions.
-- Version 2.0
--
--
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-- Changes wrt prev release.
-- 1.0 a new function addition called tc i.e twos compliment.
-- Date of Release 18 Jan 2006
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--$Author: amittal $
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--$Date: Fri Jul 11 11:14:01 2008 $
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--$Revision: 1.2 $
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--$Log: fun_pkg.vhdl.rca $
--
-- Revision: 1.2 Fri Jul 11 11:14:01 2008 amittal
-- Added Shift functions
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--$Revision: 1.2 $
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--$KeysEnd$
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

PACKAGE fun_pkg IS
 
  FUNCTION NextGray(G1:std_logic_vector) return std_logic_vector;
  --this function implements a length independent gray counter. 
  --No arithmatic operators are used.  

  FUNCTION bin2gray(B1:std_logic_vector) return std_logic_vector;
  --this function converts a binary count to gray count

  FUNCTION gray2bin(G1:std_logic_vector) return std_logic_vector;
  --this function converts a gray count to binary count

  FUNCTION crr(s1:std_logic_vector;index:integer) return std_logic_vector;
             --crr=CircularRotateRight
              --this function Circular Rotates Right 's1' by 'index'

  FUNCTION crl(s1:std_logic_vector;index:integer) return std_logic_vector;
              --crl=CircularRotateLeft
              --this function Circular Rotates Right 's1' by 'index'

  FUNCTION incr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector; 
  --This function increments an std_logic_vector type by '1', without
  --using any arithmatic

  FUNCTION dcr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector; 
  --This function decrements an std_logic_vector type by '1', without
  --using any arithmatic

  FUNCTION all_ones(s1:std_logic_vector) return std_logic; 
  --This function returns if the input vector has all ones and no zeros

  FUNCTION all_zeros(s1:std_logic_vector) return std_logic; 
  --This function returns if the input vector has all zeros and no ones

  FUNCTION mux1(a0:std_logic;a1:std_logic;sel:std_logic) return std_logic; 
  --one bit mux, handy to be used in combinational assignmets

  FUNCTION mux_vec(a0:std_logic_vector;a1:std_logic_vector;sel:std_logic) return  std_logic_vector; 
  --multi bit mux, handy to be used in combinational assignmets

  FUNCTION if_eq(s1:std_logic_vector;s2:std_logic_vector) return std_logic; 
  --returns a '1' iff s1=s2(s1 and s2 MUST be of equal no of bits

  FUNCTION inv_if_one(s1:std_logic_vector;en:std_logic) return std_logic_vector; 
  --retruns a 1's compilment of s1, if en is '1' otherwise s1 as such is returned
  FUNCTION inv(s1:std_logic_vector) return std_logic_vector; 
  --retruns a 1's compilment of s1 i.e invert of s1;

  FUNCTION myabs(s1:std_logic_vector) return std_logic_vector;
                  --this function returns an absolute value of a vector
  
  FUNCTION twos_comp(s1:std_logic_vector) return std_logic_vector; 
  --returns a twos compliment of s1
  --To make things more clear: It returns s1 itself if s1(s1'high) = '0'. Since
  --if s1(s1'high) i.e msb of s1 is '0', then the input no is +ive and hence
  --no processing is done on s1. On the other hand, if s1(s1'high) is -ive
  --then each bit in s1 is inverted and then s1 is inremented by '1'

  FUNCTION tc(s1:std_logic_vector) return std_logic_vector; 
  --returns a twos compliment of a s1.
  --No matter if the input is -ive or +ive. It will return a
  --twos compliment of the input vector.
  --IE if the input number is -ive, output will be +ive number
  --if the input number is +ive, the output will be a -ive number
  --
  FUNCTION sshr(s1:std_logic_vector) return std_logic_vector; 
  -- Signed Shift right
  -- performes shift right i.e >> i.e / 2, msb = 0, suitable for signed;
  FUNCTION zshr(s1:std_logic_vector) return std_logic_vector; 
  -- UnSigned Shift right
  -- performes shift right i.e >> i.e / 2, msb = 0, suitable for unsigned;
  FUNCTION shl(s1:std_logic_vector) return std_logic_vector; 
  -- performes shift left i.e << i.e x 2, lsb = 0;
  FUNCTION csshr(s1:std_logic_vector;s2:std_logic) return std_logic_vector; 
  -- Conditional Signed Shift right, if s2= 1, shift, otherwise return original
  -- performes shift right i.e >> i.e / 2, msb = 0, suitable for signed;
  FUNCTION czshr(s1:std_logic_vector;s2:std_logic) return std_logic_vector; 
  -- Conditional UnSigned Shift right;shift when s2 = '1'
  -- performes shift right i.e >> i.e / 2, msb = 0, suitable for unsigned;
  FUNCTION zshrn(s1:std_logic_vector;n:integer) return std_logic_vector;
  -- UnSigned Shift right by n bits
  -- performes shift right i.e >> i.e / 2, msb = 0, suitable for unsigned;
  FUNCTION sshrn(s1:std_logic_vector;nn:integer) return std_logic_vector;
  -- Signed Shift right by n bits
  -- performes shift right i.e >> i.e / 2, msb = 0, suitable for signed;
  

END fun_pkg;
PACKAGE body fun_pkg IS
--Function Declaration Section
  FUNCTION bin2gray(B1:std_logic_vector) return std_logic_vector is
    VARIABLE G1 : std_logic_vector(B1'high downto B1'low) ;
    BEGIN
    G1(G1'high):=B1(B1'high);
    for i in B1'high-1 downto B1'low loop
      G1(i) := B1(i+1) XOR B1(i);
    end loop;
    return G1;
    end bin2gray; -- end function

  FUNCTION gray2bin(G1:std_logic_vector) return std_logic_vector is
    VARIABLE B1 : std_logic_vector(G1'high downto G1'low) ;
    BEGIN
    B1(G1'high):=G1(B1'high);
    for i in G1'high-1 downto G1'low loop
      B1(i) := B1(i+1) XOR G1(i);
    end loop;
    return B1;
    end gray2bin; -- end function

  FUNCTION crr(s1:std_logic_vector;index:integer) return std_logic_vector is
              --crr=CircularRotateRight
              --this function Circular Rotates Right 's1' by 'index'
    variable z : std_logic_vector(s1'high downto s1'low);
    begin
    --pragma translate_off
    --pragma coverage_off
    if(index >= s1'length) then
    assert false
      report "crr: rotate index is greater than variable length can't rotate" severity error;
    end if;
    if(index < 0) then
    assert false
      report "crr: rotate index is negative,can't rotate" severity error;
    end if;
    --pragma coverage_on
    --pragma translate_on
    if(index = 0) then
      z:=s1;
    else
      for jj in 1 to s1'high loop
        z:= s1(jj-1 downto 0) & s1(s1'high downto jj);
        if(jj = index) then
          exit;
        end if;
      end loop;
    end if;
    return z;
  end crr; -- end function

  function crl(s1:std_logic_vector;index:integer) return std_logic_vector is
              --crl=CircularRotateLeft
              --this function Circular Rotates Right 's1' by 'index'
    variable z : std_logic_vector(s1'high downto s1'low);
    begin
    --pragma translate_off
    --pragma coverage_off
    if(index >= s1'length) then
    assert false
      report "crl: rotate index is greater than variable length can't rotate" severity error;
    end if;
    if(index < 0) then
    assert false
      report "crl: rotate index is negative,can't rotate" severity error;
    end if;
    --pragma coverage_on
    --pragma translate_on
    if(index = 0) then
      z:=s1;
    else
      for jj in 1 to s1'high loop
        z:= s1(s1'high-jj downto 0) & s1(s1'high downto s1'high-jj+1);
        if(jj = index) then
          exit;
        end if;
      end loop;
    end if;
    return z;
  end crl; -- end function




FUNCTION incr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is 
                  --this function increments a std_logic_vector type by '1' 
        VARIABLE V : std_logic_vector(s1'high downto s1'low) ; 
        VARIABLE tb : std_logic_vector(s1'high downto s1'low); 
        BEGIN 
        tb(s1'low) := en; 
        V := s1; 
        for i in (V'low + 1) to V'high loop 
            tb(i) := V(i - 1) and tb(i -1); 
        end loop; 
        for i in V'low to V'high loop 
            if(tb(i) = '1') then 
                V(i) := not(V(i)); 
            end if; 
        end loop; 
        return V; 
        end incr_vec; -- end function

FUNCTION  dcr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is 
                  --this function decrements a std_logic_vector type by '1' 
        VARIABLE V : std_logic_vector(s1'high downto s1'low) ; 
        VARIABLE tb : std_logic_vector(s1'high downto s1'low); 
        BEGIN 
        tb(s1'low) := not(en); 
        V := s1; 
        for i in (V'low + 1) to V'high loop 
            tb(i) := V(i - 1) or tb(i -1); 
        end loop; 
        for i in V'low to V'high loop 
            if(tb(i) = '0') then 
                V(i) := not(V(i)); 
            end if; 
        end loop; 
        return V; 
        end dcr_vec; -- end function

FUNCTION all_ones(s1:std_logic_vector) return std_logic is 
                  --this function tells if all bits of a vector are '1'
                  --return value Z is '1', then vector has all 1 bits
        --VARIABLE V : std_logic_vector(s1'high downto s1'low) ; 
        VARIABLE Z : std_logic; 
        BEGIN 
        Z := s1(s1'low); 
        FOR i IN (s1'low+1) to s1'high LOOP 
            Z := Z AND s1(i); 
        END LOOP;