cordic.vhd

cordic implementation in vhdl&c

--Generated by genEntity.pl Report Problems to [e-mail]
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.fun_pkg.ALL;
USE ieee.numeric_std.ALL;
use ieee.std_logic_arith.all;
USE IEEE.std_logic_signed.ALL;

ENTITY cordic IS
GENERIC ( wi : integer := 25);
  PORT (
    clk         : in  std_logic;
    rstn        : in  std_logic;
    angle       : IN  std_logic_vector(wi-1 downto 0);
    angle_valid : IN  std_logic;
    sinout      : OUT std_logic_vector(wi-1 downto 0);
    cosout      : OUT std_logic_vector(wi-1 downto 0);
    ready       : out std_logic
  );
END cordic;

ARCHITECTURE rtl OF cordic IS
--SIGNAL Declaration Section Starts
  SIGNAL itt        : integer := 0;
  SIGNAL next_itt   : integer := 0;
  SIGNAL accum      : std_logic_vector(wi-1 downto 0);
  SIGNAL next_accum : std_logic_vector(wi-1 downto 0);
  SIGNAL next_accumw: std_logic_vector(wi downto 0);
  SIGNAL re         : std_logic_vector(wi-1 downto 0);
  SIGNAL shr_re     : std_logic_vector(wi-1 downto 0);
  SIGNAL shr_re_deb : std_logic_vector(wi-1 downto 0); --for debug only
  --should be optimized away by synthesis
  SIGNAL im         : std_logic_vector(wi-1 downto 0);
  SIGNAL shr_im     : std_logic_vector(wi-1 downto 0);
  SIGNAL shr_im_deb : std_logic_vector(wi-1 downto 0); --for debug only
  SIGNAL next_re    : std_logic_vector(wi-1 downto 0);
  SIGNAL next_im    : std_logic_vector(wi-1 downto 0);
  SIGNAL alu0       : std_logic_vector(wi-1 downto 0);
  SIGNAL alu1       : std_logic_vector(wi-1 downto 0);
  SIGNAL load_re    : std_logic;
  SIGNAL load_im    : std_logic;
  SIGNAL load_accum : std_logic;
  SIGNAL incr_itt   : std_logic;
  SIGNAL add_subn0  : std_logic;
  SIGNAL add_subn1  : std_logic;
  SIGNAL add_subn2  : std_logic;
  SIGNAL mux_sel0   : std_logic;
  SIGNAL mux_sel1   : std_logic;
  SIGNAL angle_gt_accum   : std_logic;
  SIGNAL angle_valid_del   : std_logic;
  SIGNAL angle_valid_pulse   : std_logic;
  SIGNAL ready_sig   : std_logic;
  SIGNAL next_ready_sig   : std_logic;
  SIGNAL shift_im_re   : std_logic;
  type angle_array is array (12 downto 0) of std_logic_vector(wi-1 downto 0);
  SIGNAL angles : angle_array;
  --CONSTANT cordic_gain : std_logic_vector(wi-1 downto 0) := "100110110111010010111100";
  CONSTANT cordic_gain : std_logic_vector(wi-1 downto 0) := "0100110110111010010111100";
--synopsys translate_off
  SIGNAL re_real : real := 0.0; --for debug only
  SIGNAL im_real : real := 0.0; --for debug only
  SIGNAL cordic_gain_real : real := 0.0; --for debug only
  SIGNAL accum_real : real := 0.0; --for debug only
--synopsys translate_on
--SIGNAL Declaration Section Ends
  BEGIN
angles(0) <= "0010110100000000000000000"; --45
angles(1) <= "0001101010010000101001110"; --26.
angles(2) <= "0000111000001001010001110";
angles(3) <= "0000011100100000000000010";
angles(4) <= "0000001110010011100010100";
angles(5) <= "0000000111001010001101111";
angles(6) <= "0000000011100101001010011";
angles(7) <= "0000000001110010100101101";
angles(8) <= "0000000000111001010010111";
angles(9) <= "0000000000011100101001011";
angles(10) <= "0000000000001110010100101";
angles(11) <= "0000000000000111001010010";
angles(12) <= "0000000000000011100101001";
sync_reset_p : PROCESS(clk)
  BEGIN
  IF(rising_edge(clk)) then
    IF(rstn = '0') THEN
      --accum         <= (others => '0');
      itt             <= 0;
      --re            <= (others => '0');
      --im            <= (others => '0');
      ready_sig       <= '0';
    ELSE
      accum           <= next_accum;
      itt             <= next_itt;
      re              <= next_re;
      im              <= next_im;
      ready_sig       <= next_ready_sig;
      angle_valid_del <= angle_valid;
    END IF;
  END IF;
END process sync_reset_p;

angle_valid_pulse <= angle_valid and not(angle_valid_del);

itt_p : process(itt,angle_valid_pulse)
begin
  next_itt <= itt;
  if(angle_valid_pulse = '1') then
    next_itt <= 0;
  elsif(itt /= 13) then
    next_itt <= itt + 1;
  end if;
end process itt_p;

angle_gt_accum <= '1' when ((angle) > (accum)) else '0';

accum_p : process(accum,angle,itt,angles,angle_valid_pulse,angle_gt_accum)
begin
  next_accum <= accum;
  if(angle_valid_pulse = '1') then
    next_accum <= (others => '0');
  elsif(angle_gt_accum = '1' and itt /= 13) then
    next_accum <= accum + angles(itt);
  elsif(itt /= 13) then
    next_accum <= accum - angles(itt);
  end if;
end process accum_p;

shift_im_re <= '0' when itt = 0 else '1';
shr_re_deb <= sshrn(re,itt);
shr_im_deb <= sshrn(im,itt);

shift_re_im_p : process(re,im,itt)
variable shr_re_var : std_logic_vector(wi-1 downto 0);
variable shr_im_var : std_logic_vector(wi-1 downto 0);
begin
  shr_re_var := re;
  shr_im_var := im;
  if(itt /= 0 ) then
    for ii in 1 to re'high+1 loop
      shr_re_var := sshrn(shr_re_var,1);
      shr_im_var := sshrn(shr_im_var,1);
      if(ii=itt) then
        exit;
      end if;
    end loop;
  end if;
  shr_re <= shr_re_var;
  shr_im <= shr_im_var;
end process shift_re_im_p;

alu0 <= (re-shr_im) when angle_gt_accum  = '1' else (re+shr_im);
alu1 <= (im + shr_re) when angle_gt_accum = '1' else (im - shr_re);

next_re <= alu0 when angle_valid_pulse = '0' else cordic_gain;
next_im <= alu1 when angle_valid_pulse = '0' else (others => '0');

next_ready_sig <= '1' when (rstn = '0' or itt = 12) else '0';

ready <= ready_sig;

cosout <= (others => '0') when ready_sig = '0' else re;
sinout <= (others => '0') when ready_sig = '0' else im;


--synopsys translate_off
re_real <= 1.0 * real(conv_integer(re)) * 596.0464477539;
im_real <= 1.0 * real(conv_integer(im)) * 596.0464477539;
accum_real <= 1.0 * real(conv_integer(accum)) * 76293.9453124992;
cordic_gain_real <= 1.0 * real(conv_integer(cordic_gain))* 596.0464477539;
--synopsys translate_on

  END rtl;