📄 siso_for.tf

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`timescale 1ns/1nsmodule t;reg Clock, Clear, SI;wire SO;    SISO_Shift_Register m (.Clock(Clock), .Clear(Clear), .SI(SI), .SO(SO));    // Enter fixture code here    initial
    begin
    #0
	    Clock   = 0;
       Clear   = 1;

    #50
	    Clock   = 1;



    #50
	    Clock   = 0;
       Clear   = 0;
       SI      = 1;

    #50
	    Clock   = 1;



    #50
	    Clock   = 0;
       SI      = 1;

    #50
	    Clock   = 1;



    #50
	    Clock   = 0;
       SI      = 0;

    #50
	    Clock   = 1;



    #50
	    Clock   = 0;
       SI      = 1;

    #50
	    Clock   = 1;





    #50
	    Clock   = 0;
       SI      = 0;

    #50
	    Clock   = 1;






    #50
	    Clock   = 0;
       SI      = 0;

    #50
	    Clock   = 1;



    #50
	    Clock   = 0;
       SI      = 1;

    #50
	    Clock   = 1;



    #50
	    Clock   = 0;
       SI      = 0;

    #50
	    Clock   = 1;






    #50
	    Clock   = 0;
       SI      = 1;

    #50
	    Clock   = 1;


    #50
	    Clock   = 0;
       SI      = 0;

    #50
	    Clock   = 1;
    #50
	    Clock   = 0;
       SI      = 0;

    #50
	    Clock   = 1;
    #50
	    Clock   = 0;
       SI      = 0;

    #50
	    Clock   = 1;
    #50
	    Clock   = 0;
       SI      = 0;

    #50
	    Clock   = 1;




    #50
	    Clock   = 0;
       SI      = 1;

    #50
	    Clock   = 1;
    #50
	    Clock   = 0;
       SI      = 1;

    #50
	    Clock   = 1;
    #50
	    Clock   = 0;
       SI      = 1;

    #50
	    Clock   = 1;
    #50
	    Clock   = 0;
       SI      = 1;

    #50
	    Clock   = 1;



    #50
	    Clock  = 0;
  end
endmodule // t

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