_primary.vhd

一些程式 請大家 多多關照.........

library verilog;
use verilog.vl_types.all;
entity Is_Valid_SUB_Inst is
    generic(
        IMMEDIATE       : integer := 0;
        DIRECT          : integer := 1;
        SUBA_imm        : integer := 128;
        SUBA_dir        : integer := 144;
        SUBB_imm        : integer := 192;
        SUBB_dir        : integer := 208
    );
    port(
        Inst            : in     vl_logic_vector(7 downto 0);
        Mode            : in     vl_logic_vector(1 downto 0);
        Valid           : out    vl_logic;
        NonValid        : out    vl_logic
    );
end Is_Valid_SUB_Inst;