_primary.vhd

一些程式 請大家 多多關照.........

library verilog;
use verilog.vl_types.all;
entity Sign_Extend is
    port(
        SignExtend      : in     vl_logic;
        Word            : in     vl_logic_vector(7 downto 0);
        Double          : out    vl_logic_vector(15 downto 0)
    );
end Sign_Extend;