paobiao.map.eqn

一个具有“百分秒

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L42Q is MSH[0]~reg0
--operation mode is normal

A1L42Q_lut_out = !A1L42Q;
A1L42Q = DFFEAS(A1L42Q_lut_out, CLK, !CLR, , A1L82, , , , );


--A1L62Q is MSH[1]~reg0
--operation mode is normal

A1L62Q_lut_out = A1L62Q & (!A1L42Q) # !A1L62Q & A1L42Q & (A1L03Q # !A1L23Q);
A1L62Q = DFFEAS(A1L62Q_lut_out, CLK, !CLR, , A1L82, , , , );


--A1L03Q is MSH[2]~reg0
--operation mode is normal

A1L03Q_lut_out = !A1L03Q;
A1L03Q = DFFEAS(A1L03Q_lut_out, CLK, !CLR, , A1L92, , , , );


--A1L23Q is MSH[3]~reg0
--operation mode is normal

A1L23Q_lut_out = A1L23Q & (A1L62Q $ A1L03Q # !A1L42Q) # !A1L23Q & A1L62Q & A1L03Q & A1L42Q;
A1L23Q = DFFEAS(A1L23Q_lut_out, CLK, !CLR, , A1L82, , , , );


--A1L53Q is MSL[0]~reg0
--operation mode is normal

A1L53Q_lut_out = !A1L53Q;
A1L53Q = DFFEAS(A1L53Q_lut_out, CLK, !CLR, , !PAUSE, , , , );


--A1L73Q is MSL[1]~reg0
--operation mode is normal

A1L73Q_lut_out = A1L73Q & (!A1L53Q) # !A1L73Q & A1L53Q & (A1L04Q # !A1L24Q);
A1L73Q = DFFEAS(A1L73Q_lut_out, CLK, !CLR, , !PAUSE, , , , );


--A1L04Q is MSL[2]~reg0
--operation mode is normal

A1L04Q_lut_out = !A1L04Q;
A1L04Q = DFFEAS(A1L04Q_lut_out, CLK, !CLR, , A1L93, , , , );


--A1L24Q is MSL[3]~reg0
--operation mode is normal

A1L24Q_lut_out = A1L24Q & (A1L73Q $ A1L04Q # !A1L53Q) # !A1L24Q & A1L73Q & A1L04Q & A1L53Q;
A1L24Q = DFFEAS(A1L24Q_lut_out, CLK, !CLR, , !PAUSE, , , , );


--A1L64Q is SH[0]~reg0
--operation mode is normal

A1L64Q_lut_out = !A1L64Q;
A1L64Q = DFFEAS(A1L64Q_lut_out, cn1, !CLR, , A1L86, , , , );


--A1L84Q is SH[1]~reg0
--operation mode is normal

A1L84Q_lut_out = A1L84Q & (!A1L64Q) # !A1L84Q & A1L64Q & (A1L35Q # !A1L05Q);
A1L84Q = DFFEAS(A1L84Q_lut_out, cn1, !CLR, , A1L86, , , , );


--A1L05Q is SH[2]~reg0
--operation mode is normal

A1L05Q_lut_out = A1L84Q & (A1L05Q $ A1L64Q) # !A1L84Q & A1L05Q & (A1L35Q # !A1L64Q);
A1L05Q = DFFEAS(A1L05Q_lut_out, cn1, !CLR, , A1L86, , , , );


--A1L35Q is SH[3]~reg0
--operation mode is normal

A1L35Q_lut_out = !A1L35Q;
A1L35Q = DFFEAS(A1L35Q_lut_out, cn1, !CLR, , A1L25, , , , );


--A1L65Q is SL[0]~reg0
--operation mode is normal

A1L65Q_lut_out = !A1L65Q;
A1L65Q = DFFEAS(A1L65Q_lut_out, cn1, !CLR, , , , , , );


--A1L85Q is SL[1]~reg0
--operation mode is normal

A1L85Q_lut_out = A1L85Q & (!A1L65Q) # !A1L85Q & A1L65Q & (A1L06Q # !A1L26Q);
A1L85Q = DFFEAS(A1L85Q_lut_out, cn1, !CLR, , , , , , );


--A1L06Q is SL[2]~reg0
--operation mode is normal

A1L06Q_lut_out = !A1L06Q;
A1L06Q = DFFEAS(A1L06Q_lut_out, cn1, !CLR, , A1L36, , , , );


--A1L26Q is SL[3]~reg0
--operation mode is normal

A1L26Q_lut_out = A1L26Q & (A1L85Q $ A1L06Q # !A1L65Q) # !A1L26Q & A1L85Q & A1L06Q & A1L65Q;
A1L26Q = DFFEAS(A1L26Q_lut_out, cn1, !CLR, , , , , , );


--A1L5Q is MH[0]~reg0
--operation mode is normal

A1L5Q_lut_out = !A1L5Q;
A1L5Q = DFFEAS(A1L5Q_lut_out, cn2, !CLR, , A1L96, , , , );


--A1L7Q is MH[1]~reg0
--operation mode is normal

A1L7Q_lut_out = A1L7Q & (!A1L5Q) # !A1L7Q & A1L5Q & (A1L21Q # !A1L9Q);
A1L7Q = DFFEAS(A1L7Q_lut_out, cn2, !CLR, , A1L96, , , , );


--A1L9Q is MH[2]~reg0
--operation mode is normal

A1L9Q_lut_out = A1L7Q & (A1L9Q $ A1L5Q) # !A1L7Q & A1L9Q & (A1L21Q # !A1L5Q);
A1L9Q = DFFEAS(A1L9Q_lut_out, cn2, !CLR, , A1L96, , , , );


--A1L21Q is MH[3]~reg0
--operation mode is normal

A1L21Q_lut_out = !A1L21Q;
A1L21Q = DFFEAS(A1L21Q_lut_out, cn2, !CLR, , A1L11, , , , );


--A1L51Q is ML[0]~reg0
--operation mode is normal

A1L51Q_lut_out = !A1L51Q;
A1L51Q = DFFEAS(A1L51Q_lut_out, cn2, !CLR, , , , , , );


--A1L71Q is ML[1]~reg0
--operation mode is normal

A1L71Q_lut_out = A1L71Q & (!A1L51Q) # !A1L71Q & A1L51Q & (A1L91Q # !A1L12Q);
A1L71Q = DFFEAS(A1L71Q_lut_out, cn2, !CLR, , , , , , );


--A1L91Q is ML[2]~reg0
--operation mode is normal

A1L91Q_lut_out = !A1L91Q;
A1L91Q = DFFEAS(A1L91Q_lut_out, cn2, !CLR, , A1L46, , , , );


--A1L12Q is ML[3]~reg0
--operation mode is normal

A1L12Q_lut_out = A1L12Q & (A1L71Q $ A1L91Q # !A1L51Q) # !A1L12Q & A1L71Q & A1L91Q & A1L51Q;
A1L12Q = DFFEAS(A1L12Q_lut_out, cn2, !CLR, , , , , , );


--A1L76 is reduce_nor~127
--operation mode is normal

A1L76 = A1L73Q # A1L04Q # !A1L24Q # !A1L53Q;


--A1L82 is MSH[2]~8
--operation mode is normal

A1L82 = !PAUSE & !A1L76;


--A1L92 is MSH[2]~132
--operation mode is normal

A1L92 = A1L42Q & A1L62Q & !PAUSE & !A1L76;


--A1L93 is MSL[2]~112
--operation mode is normal

A1L93 = A1L53Q & A1L73Q & (!PAUSE);


--cn1 is cn1
--operation mode is normal

cn1_lut_out = !A1L76 & (cn1 # !A1L07);
cn1 = DFFEAS(cn1_lut_out, CLK, !CLR, , !PAUSE, , , , );


--A1L86 is reduce_nor~128
--operation mode is normal

A1L86 = !A1L85Q & !A1L06Q & A1L65Q & A1L26Q;


--A1L25 is SH[3]~121
--operation mode is normal

A1L25 = A1L64Q & A1L84Q & A1L05Q & A1L86;


--A1L36 is add~510
--operation mode is normal

A1L36 = A1L65Q & A1L85Q;


--cn2 is cn2
--operation mode is normal

cn2_lut_out = A1L86 & (cn2 # !A1L17);
cn2 = DFFEAS(cn2_lut_out, cn1, !CLR, , , , , , );


--A1L96 is reduce_nor~129
--operation mode is normal

A1L96 = !A1L71Q & !A1L91Q & A1L51Q & A1L12Q;


--A1L11 is MH[3]~121
--operation mode is normal

A1L11 = A1L5Q & A1L7Q & A1L9Q & A1L96;


--A1L46 is add~511
--operation mode is normal

A1L46 = A1L51Q & A1L71Q;


--A1L07 is reduce_nor~130
--operation mode is normal

A1L07 = A1L62Q # A1L03Q # !A1L23Q # !A1L42Q;


--A1L17 is reduce_nor~131
--operation mode is normal

A1L17 = A1L84Q # A1L35Q # !A1L05Q # !A1L64Q;


--CLK is CLK
--operation mode is input

CLK = INPUT();


--CLR is CLR
--operation mode is input

CLR = INPUT();


--PAUSE is PAUSE
--operation mode is input

PAUSE = INPUT();


--MSH[0] is MSH[0]
--operation mode is output

MSH[0] = OUTPUT(A1L42Q);


--MSH[1] is MSH[1]
--operation mode is output

MSH[1] = OUTPUT(A1L62Q);


--MSH[2] is MSH[2]
--operation mode is output

MSH[2] = OUTPUT(A1L03Q);


--MSH[3] is MSH[3]
--operation mode is output

MSH[3] = OUTPUT(A1L23Q);


--MSL[0] is MSL[0]
--operation mode is output

MSL[0] = OUTPUT(A1L53Q);


--MSL[1] is MSL[1]
--operation mode is output

MSL[1] = OUTPUT(A1L73Q);


--MSL[2] is MSL[2]
--operation mode is output

MSL[2] = OUTPUT(A1L04Q);


--MSL[3] is MSL[3]
--operation mode is output

MSL[3] = OUTPUT(A1L24Q);


--SH[0] is SH[0]
--operation mode is output

SH[0] = OUTPUT(A1L64Q);


--SH[1] is SH[1]
--operation mode is output

SH[1] = OUTPUT(A1L84Q);


--SH[2] is SH[2]
--operation mode is output

SH[2] = OUTPUT(A1L05Q);


--SH[3] is SH[3]
--operation mode is output

SH[3] = OUTPUT(A1L35Q);


--SL[0] is SL[0]
--operation mode is output

SL[0] = OUTPUT(A1L65Q);


--SL[1] is SL[1]
--operation mode is output

SL[1] = OUTPUT(A1L85Q);


--SL[2] is SL[2]
--operation mode is output

SL[2] = OUTPUT(A1L06Q);


--SL[3] is SL[3]
--operation mode is output

SL[3] = OUTPUT(A1L26Q);


--MH[0] is MH[0]
--operation mode is output

MH[0] = OUTPUT(A1L5Q);


--MH[1] is MH[1]
--operation mode is output

MH[1] = OUTPUT(A1L7Q);


--MH[2] is MH[2]
--operation mode is output

MH[2] = OUTPUT(A1L9Q);


--MH[3] is MH[3]
--operation mode is output

MH[3] = OUTPUT(A1L21Q);


--ML[0] is ML[0]
--operation mode is output

ML[0] = OUTPUT(A1L51Q);


--ML[1] is ML[1]
--operation mode is output

ML[1] = OUTPUT(A1L71Q);


--ML[2] is ML[2]
--operation mode is output

ML[2] = OUTPUT(A1L91Q);


--ML[3] is ML[3]
--operation mode is output

ML[3] = OUTPUT(A1L12Q);