dds.hier_info

数字信号源

|dds
data[0] => ADD_A[0].DATAIN
data[1] => ADD_A[1].DATAIN
data[2] => ADD_A[2].DATAIN
data[3] => ADD_A[3].DATAIN
data[4] => ADD_A[4].DATAIN
data[5] => ADD_A[5].DATAIN
data[6] => ADD_A[6].DATAIN
data[7] => ADD_A[7].DATAIN
data[8] => ADD_A[8].DATAIN
data[9] => ADD_A[9].DATAIN
data[10] => ADD_A[10].DATAIN
data[11] => ADD_A[11].DATAIN
data[12] => ADD_A[12].DATAIN
data[13] => ADD_A[13].DATAIN
data[14] => ADD_A[14].DATAIN
data[15] => ADD_A[15].DATAIN
data[16] => ADD_A[16].DATAIN
data[17] => ADD_A[17].DATAIN
data[18] => ADD_A[18].DATAIN
data[19] => ADD_A[19].DATAIN
data[20] => ADD_A[20].DATAIN
data[21] => ADD_A[21].DATAIN
data[22] => ADD_A[22].DATAIN
data[23] => ADD_A[23].DATAIN
data[24] => ADD_A[24].DATAIN
data[25] => ADD_A[25].DATAIN
data[26] => ADD_A[26].DATAIN
data[27] => ADD_A[27].DATAIN
data[28] => ADD_A[28].DATAIN
data[29] => ADD_A[29].DATAIN
data[30] => ADD_A[30].DATAIN
data[31] => ADD_A[31].DATAIN
we => ADD_A[31].ENA
we => ADD_A[30].ENA
we => ADD_A[29].ENA
we => ADD_A[28].ENA
we => ADD_A[27].ENA
we => ADD_A[26].ENA
we => ADD_A[25].ENA
we => ADD_A[24].ENA
we => ADD_A[23].ENA
we => ADD_A[22].ENA
we => ADD_A[21].ENA
we => ADD_A[20].ENA
we => ADD_A[19].ENA
we => ADD_A[18].ENA
we => ADD_A[17].ENA
we => ADD_A[16].ENA
we => ADD_A[15].ENA
we => ADD_A[14].ENA
we => ADD_A[13].ENA
we => ADD_A[12].ENA
we => ADD_A[11].ENA
we => ADD_A[10].ENA
we => ADD_A[9].ENA
we => ADD_A[8].ENA
we => ADD_A[7].ENA
we => ADD_A[6].ENA
we => ADD_A[5].ENA
we => ADD_A[4].ENA
we => ADD_A[3].ENA
we => ADD_A[2].ENA
we => ADD_A[1].ENA
we => ADD_A[0].ENA
clk => clk~0.IN2
ce => ADD_B~9.OUTPUTSELECT
ce => ADD_B~8.OUTPUTSELECT
ce => ADD_B~7.OUTPUTSELECT
ce => ADD_B~6.OUTPUTSELECT
ce => ADD_B~5.OUTPUTSELECT
ce => ADD_B~4.OUTPUTSELECT
ce => ADD_B~3.OUTPUTSELECT
ce => ADD_B~2.OUTPUTSELECT
ce => ADD_B~1.OUTPUTSELECT
ce => ADD_B~0.OUTPUTSELECT
ce => ADD_B[21].ENA
ce => ADD_B[20].ENA
ce => ADD_B[19].ENA
ce => ADD_B[18].ENA
ce => ADD_B[17].ENA
ce => ADD_B[16].ENA
ce => ADD_B[15].ENA
ce => ADD_B[14].ENA
ce => ADD_B[13].ENA
ce => ADD_B[12].ENA
ce => ADD_B[11].ENA
ce => ADD_B[10].ENA
ce => ADD_B[9].ENA
ce => ADD_B[8].ENA
ce => ADD_B[7].ENA
ce => ADD_B[6].ENA
ce => ADD_B[5].ENA
ce => ADD_B[4].ENA
ce => ADD_B[3].ENA
ce => ADD_B[2].ENA
ce => ADD_B[1].ENA
ce => ADD_B[0].ENA
ce => cose_DR[15].ENA
ce => cose_DR[14].ENA
ce => cose_DR[13].ENA
ce => cose_DR[12].ENA
ce => cose_DR[11].ENA
ce => cose_DR[10].ENA
ce => cose_DR[9].ENA
ce => cose_DR[8].ENA
ce => cose_DR[7].ENA
ce => cose_DR[6].ENA
ce => cose_DR[5].ENA
ce => cose_DR[4].ENA
ce => cose_DR[3].ENA
ce => cose_DR[2].ENA
ce => cose_DR[1].ENA
ce => cose_DR[0].ENA
ce => sine_DR[15].ENA
ce => sine_DR[14].ENA
ce => sine_DR[13].ENA
ce => sine_DR[12].ENA
ce => sine_DR[11].ENA
ce => sine_DR[10].ENA
ce => sine_DR[9].ENA
ce => sine_DR[8].ENA
ce => sine_DR[7].ENA
ce => sine_DR[6].ENA
ce => sine_DR[5].ENA
ce => sine_DR[4].ENA
ce => sine_DR[3].ENA
ce => sine_DR[2].ENA
ce => sine_DR[1].ENA
ce => sine_DR[0].ENA
reset => ADD_A[31].ACLR
reset => ADD_A[30].ACLR
reset => ADD_A[29].ACLR
reset => ADD_A[28].ACLR
reset => ADD_A[27].ACLR
reset => ADD_A[26].ACLR
reset => ADD_A[25].ACLR
reset => ADD_A[24].ACLR
reset => ADD_A[23].ACLR
reset => ADD_A[22].ACLR
reset => ADD_A[21].ACLR
reset => ADD_A[20].ACLR
reset => ADD_A[19].ACLR
reset => ADD_A[18].ACLR
reset => ADD_A[17].ACLR
reset => ADD_A[16].ACLR
reset => ADD_A[15].ACLR
reset => ADD_A[14].ACLR
reset => ADD_A[13].ACLR
reset => ADD_A[12].ACLR
reset => ADD_A[11].ACLR
reset => ADD_A[10].ACLR
reset => ADD_A[9].ACLR
reset => ADD_A[8].ACLR
reset => ADD_A[7].ACLR
reset => ADD_A[6].ACLR
reset => ADD_A[5].ACLR
reset => ADD_A[4].ACLR
reset => ADD_A[3].ACLR
reset => ADD_A[2].ACLR
reset => ADD_A[1].ACLR
reset => ADD_A[0].ACLR
reset => ADD_B[31].ACLR
reset => ADD_B[30].ACLR
reset => ADD_B[29].ACLR
reset => ADD_B[28].ACLR
reset => ADD_B[27].ACLR
reset => ADD_B[26].ACLR
reset => ADD_B[25].ACLR
reset => ADD_B[24].ACLR
reset => ADD_B[23].ACLR
reset => ADD_B[22].ACLR
reset => ADD_B[21].ACLR
reset => ADD_B[20].ACLR
reset => ADD_B[19].ACLR
reset => ADD_B[18].ACLR
reset => ADD_B[17].ACLR
reset => ADD_B[16].ACLR
reset => ADD_B[15].ACLR
reset => ADD_B[14].ACLR
reset => ADD_B[13].ACLR
reset => ADD_B[12].ACLR
reset => ADD_B[11].ACLR
reset => ADD_B[10].ACLR
reset => ADD_B[9].ACLR
reset => ADD_B[8].ACLR
reset => ADD_B[7].ACLR
reset => ADD_B[6].ACLR
reset => ADD_B[5].ACLR
reset => ADD_B[4].ACLR
reset => ADD_B[3].ACLR
reset => ADD_B[2].ACLR
reset => ADD_B[1].ACLR
reset => ADD_B[0].ACLR
reset => cose_DR[15].ACLR
reset => cose_DR[14].ACLR
reset => cose_DR[13].ACLR
reset => cose_DR[12].ACLR
reset => cose_DR[11].ACLR
reset => cose_DR[10].ACLR
reset => cose_DR[9].ACLR
reset => cose_DR[8].ACLR
reset => cose_DR[7].ACLR
reset => cose_DR[6].ACLR
reset => cose_DR[5].ACLR
reset => cose_DR[4].ACLR
reset => cose_DR[3].ACLR
reset => cose_DR[2].ACLR
reset => cose_DR[1].ACLR
reset => cose_DR[0].ACLR
reset => sine_DR[15].ACLR
reset => sine_DR[14].ACLR
reset => sine_DR[13].ACLR
reset => sine_DR[12].ACLR
reset => sine_DR[11].ACLR
reset => sine_DR[10].ACLR
reset => sine_DR[9].ACLR
reset => sine_DR[8].ACLR
reset => sine_DR[7].ACLR
reset => sine_DR[6].ACLR
reset => sine_DR[5].ACLR
reset => sine_DR[4].ACLR
reset => sine_DR[3].ACLR
reset => sine_DR[2].ACLR
reset => sine_DR[1].ACLR
reset => sine_DR[0].ACLR
sine[0] <= sine_DR[0].DB_MAX_OUTPUT_PORT_TYPE
sine[1] <= sine_DR[1].DB_MAX_OUTPUT_PORT_TYPE
sine[2] <= sine_DR[2].DB_MAX_OUTPUT_PORT_TYPE
sine[3] <= sine_DR[3].DB_MAX_OUTPUT_PORT_TYPE
sine[4] <= sine_DR[4].DB_MAX_OUTPUT_PORT_TYPE
sine[5] <= sine_DR[5].DB_MAX_OUTPUT_PORT_TYPE
sine[6] <= sine_DR[6].DB_MAX_OUTPUT_PORT_TYPE
sine[7] <= sine_DR[7].DB_MAX_OUTPUT_PORT_TYPE
sine[8] <= sine_DR[8].DB_MAX_OUTPUT_PORT_TYPE
sine[9] <= sine_DR[9].DB_MAX_OUTPUT_PORT_TYPE
sine[10] <= sine_DR[10].DB_MAX_OUTPUT_PORT_TYPE
sine[11] <= sine_DR[11].DB_MAX_OUTPUT_PORT_TYPE
sine[12] <= sine_DR[12].DB_MAX_OUTPUT_PORT_TYPE
sine[13] <= sine_DR[13].DB_MAX_OUTPUT_PORT_TYPE
sine[14] <= sine_DR[14].DB_MAX_OUTPUT_PORT_TYPE
sine[15] <= sine_DR[15].DB_MAX_OUTPUT_PORT_TYPE
cose[0] <= cose_DR[0].DB_MAX_OUTPUT_PORT_TYPE
cose[1] <= cose_DR[1].DB_MAX_OUTPUT_PORT_TYPE
cose[2] <= cose_DR[2].DB_MAX_OUTPUT_PORT_TYPE
cose[3] <= cose_DR[3].DB_MAX_OUTPUT_PORT_TYPE
cose[4] <= cose_DR[4].DB_MAX_OUTPUT_PORT_TYPE
cose[5] <= cose_DR[5].DB_MAX_OUTPUT_PORT_TYPE
cose[6] <= cose_DR[6].DB_MAX_OUTPUT_PORT_TYPE
cose[7] <= cose_DR[7].DB_MAX_OUTPUT_PORT_TYPE
cose[8] <= cose_DR[8].DB_MAX_OUTPUT_PORT_TYPE
cose[9] <= cose_DR[9].DB_MAX_OUTPUT_PORT_TYPE
cose[10] <= cose_DR[10].DB_MAX_OUTPUT_PORT_TYPE
cose[11] <= cose_DR[11].DB_MAX_OUTPUT_PORT_TYPE
cose[12] <= cose_DR[12].DB_MAX_OUTPUT_PORT_TYPE
cose[13] <= cose_DR[13].DB_MAX_OUTPUT_PORT_TYPE
cose[14] <= cose_DR[14].DB_MAX_OUTPUT_PORT_TYPE
cose[15] <= cose_DR[15].DB_MAX_OUTPUT_PORT_TYPE


|dds|rom_cose:cose1
address[0] => address[0]~9.IN1
address[1] => address[1]~8.IN1
address[2] => address[2]~7.IN1
address[3] => address[3]~6.IN1
address[4] => address[4]~5.IN1
address[5] => address[5]~4.IN1
address[6] => address[6]~3.IN1
address[7] => address[7]~2.IN1
address[8] => address[8]~1.IN1
address[9] => address[9]~0.IN1
clock => clock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a
q[8] <= altsyncram:altsyncram_component.q_a
q[9] <= altsyncram:altsyncram_component.q_a
q[10] <= altsyncram:altsyncram_component.q_a
q[11] <= altsyncram:altsyncram_component.q_a
q[12] <= altsyncram:altsyncram_component.q_a
q[13] <= altsyncram:altsyncram_component.q_a
q[14] <= altsyncram:altsyncram_component.q_a
q[15] <= altsyncram:altsyncram_component.q_a


|dds|rom_cose:cose1|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_a[12] => ~NO_FANOUT~
data_a[13] => ~NO_FANOUT~
data_a[14] => ~NO_FANOUT~
data_a[15] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_2571:auto_generated.address_a[0]
address_a[1] => altsyncram_2571:auto_generated.address_a[1]
address_a[2] => altsyncram_2571:auto_generated.address_a[2]
address_a[3] => altsyncram_2571:auto_generated.address_a[3]
address_a[4] => altsyncram_2571:auto_generated.address_a[4]
address_a[5] => altsyncram_2571:auto_generated.address_a[5]
address_a[6] => altsyncram_2571:auto_generated.address_a[6]
address_a[7] => altsyncram_2571:auto_generated.address_a[7]
address_a[8] => altsyncram_2571:auto_generated.address_a[8]
address_a[9] => altsyncram_2571:auto_generated.address_a[9]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_2571:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_2571:auto_generated.q_a[0]
q_a[1] <= altsyncram_2571:auto_generated.q_a[1]
q_a[2] <= altsyncram_2571:auto_generated.q_a[2]
q_a[3] <= altsyncram_2571:auto_generated.q_a[3]
q_a[4] <= altsyncram_2571:auto_generated.q_a[4]
q_a[5] <= altsyncram_2571:auto_generated.q_a[5]
q_a[6] <= altsyncram_2571:auto_generated.q_a[6]
q_a[7] <= altsyncram_2571:auto_generated.q_a[7]
q_a[8] <= altsyncram_2571:auto_generated.q_a[8]
q_a[9] <= altsyncram_2571:auto_generated.q_a[9]
q_a[10] <= altsyncram_2571:auto_generated.q_a[10]
q_a[11] <= altsyncram_2571:auto_generated.q_a[11]
q_a[12] <= altsyncram_2571:auto_generated.q_a[12]
q_a[13] <= altsyncram_2571:auto_generated.q_a[13]
q_a[14] <= altsyncram_2571:auto_generated.q_a[14]
q_a[15] <= altsyncram_2571:auto_generated.q_a[15]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4