dds.tan.qmsg

数字信号源

{ "Info" "ITDB_FULL_TCO_RESULT" "clk cose\[9\] cose_DR\[9\] 6.917 ns register " "Info: tco from clock \"clk\" to destination pin \"cose\[9\]\" through register \"cose_DR\[9\]\" is 6.917 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.330 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.330 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_H2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk~clkctrl 2 COMB CLKCTRL_G2 208 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 208; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.692 ns) + CELL(0.537 ns) 2.330 ns cose_DR\[9\] 3 REG LCFF_X10_Y6_N13 1 " "Info: 3: + IC(0.692 ns) + CELL(0.537 ns) = 2.330 ns; Loc. = LCFF_X10_Y6_N13; Fanout = 1; REG Node = 'cose_DR\[9\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.229 ns" { clk~clkctrl cose_DR[9] } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 65.06 % ) " "Info: Total cell delay = 1.516 ns ( 65.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.814 ns ( 34.94 % ) " "Info: Total interconnect delay = 0.814 ns ( 34.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.330 ns" { clk clk~clkctrl cose_DR[9] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.330 ns" { clk {} clk~combout {} clk~clkctrl {} cose_DR[9] {} } { 0.000ns 0.000ns 0.122ns 0.692ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "dds.v" "" { Text "C:/altera/dds/dds.v" 64 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.337 ns + Longest register pin " "Info: + Longest register to pin delay is 4.337 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cose_DR\[9\] 1 REG LCFF_X10_Y6_N13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X10_Y6_N13; Fanout = 1; REG Node = 'cose_DR\[9\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cose_DR[9] } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.715 ns) + CELL(2.622 ns) 4.337 ns cose\[9\] 2 PIN PIN_K16 0 " "Info: 2: + IC(1.715 ns) + CELL(2.622 ns) = 4.337 ns; Loc. = PIN_K16; Fanout = 0; PIN Node = 'cose\[9\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.337 ns" { cose_DR[9] cose[9] } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.622 ns ( 60.46 % ) " "Info: Total cell delay = 2.622 ns ( 60.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.715 ns ( 39.54 % ) " "Info: Total interconnect delay = 1.715 ns ( 39.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.337 ns" { cose_DR[9] cose[9] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.337 ns" { cose_DR[9] {} cose[9] {} } { 0.000ns 1.715ns } { 0.000ns 2.622ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.330 ns" { clk clk~clkctrl cose_DR[9] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.330 ns" { clk {} clk~combout {} clk~clkctrl {} cose_DR[9] {} } { 0.000ns 0.000ns 0.122ns 0.692ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.337 ns" { cose_DR[9] cose[9] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.337 ns" { cose_DR[9] {} cose[9] {} } { 0.000ns 1.715ns } { 0.000ns 2.622ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "ADD_A\[15\] data\[15\] clk -3.576 ns register " "Info: th for register \"ADD_A\[15\]\" (data pin = \"data\[15\]\", clock pin = \"clk\") is -3.576 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.334 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.334 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_H2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk~clkctrl 2 COMB CLKCTRL_G2 208 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 208; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.696 ns) + CELL(0.537 ns) 2.334 ns ADD_A\[15\] 3 REG LCFF_X13_Y6_N19 2 " "Info: 3: + IC(0.696 ns) + CELL(0.537 ns) = 2.334 ns; Loc. = LCFF_X13_Y6_N19; Fanout = 2; REG Node = 'ADD_A\[15\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.233 ns" { clk~clkctrl ADD_A[15] } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 64.95 % ) " "Info: Total cell delay = 1.516 ns ( 64.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.818 ns ( 35.05 % ) " "Info: Total interconnect delay = 0.818 ns ( 35.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.334 ns" { clk clk~clkctrl ADD_A[15] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.334 ns" { clk {} clk~combout {} clk~clkctrl {} ADD_A[15] {} } { 0.000ns 0.000ns 0.122ns 0.696ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "dds.v" "" { Text "C:/altera/dds/dds.v" 48 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.176 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.176 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.822 ns) 0.822 ns data\[15\] 1 PIN PIN_K5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.822 ns) = 0.822 ns; Loc. = PIN_K5; Fanout = 1; PIN Node = 'data\[15\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[15] } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.121 ns) + CELL(0.149 ns) 6.092 ns ADD_A\[15\]~feeder 2 COMB LCCOMB_X13_Y6_N18 1 " "Info: 2: + IC(5.121 ns) + CELL(0.149 ns) = 6.092 ns; Loc. = LCCOMB_X13_Y6_N18; Fanout = 1; COMB Node = 'ADD_A\[15\]~feeder'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.270 ns" { data[15] ADD_A[15]~feeder } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.176 ns ADD_A\[15\] 3 REG LCFF_X13_Y6_N19 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.176 ns; Loc. = LCFF_X13_Y6_N19; Fanout = 2; REG Node = 'ADD_A\[15\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { ADD_A[15]~feeder ADD_A[15] } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.055 ns ( 17.08 % ) " "Info: Total cell delay = 1.055 ns ( 17.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.121 ns ( 82.92 % ) " "Info: Total interconnect delay = 5.121 ns ( 82.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.176 ns" { data[15] ADD_A[15]~feeder ADD_A[15] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.176 ns" { data[15] {} data[15]~combout {} ADD_A[15]~feeder {} ADD_A[15] {} } { 0.000ns 0.000ns 5.121ns 0.000ns } { 0.000ns 0.822ns 0.149ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.334 ns" { clk clk~clkctrl ADD_A[15] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.334 ns" { clk {} clk~combout {} clk~clkctrl {} ADD_A[15] {} } { 0.000ns 0.000ns 0.122ns 0.696ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.176 ns" { data[15] ADD_A[15]~feeder ADD_A[15] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.176 ns" { data[15] {} data[15]~combout {} ADD_A[15]~feeder {} ADD_A[15] {} } { 0.000ns 0.000ns 5.121ns 0.000ns } { 0.000ns 0.822ns 0.149ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "115 " "Info: Allocated 115 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 21 09:40:07 2008 " "Info: Processing ended: Fri Nov 21 09:40:07 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}