test_dds.v

来自「数字信号源」· Verilog 代码 · 共 28 行

`timescale 1ns/1ps
module test_dds();
parameter CLK_CYCLE =20;
parameter CLK_HCYCLE=10;

reg we,ce;
reg rst;
reg clk;
reg [31:0]data;
wire [15:0] sine;
wire [15:0] cose;

dds dut(.we(we),.ce(ce),.clk(clk),.reset(rst),.data(data),   .sine(sine),.cose(cose)  );

initial
begin
	clk=1'b1;
	rst=1'b0;
	we=1'b0;
	ce=1'b1;
	data=32'b0;
	#(10*CLK_CYCLE+CLK_HCYCLE) rst=1'b1;
	
end
always #CLK_HCYCLE clk=~clk;
initial
  $monitor($time,rst,,clk,,we,,ce,,data,,sine,,cose);
endmodule