dds.vo

数字信号源

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 7.2 Build 151 09/26/2007 SJ Web Edition"

// DATE "11/28/2008 15:54:08"

// 
// Device: Altera EP1AGX60DF780C6 Package FBGA780
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module dds (
	data,
	we,
	clk,
	ce,
	reset,
	sine,
	cose);
input 	[31:0] data;
input 	we;
input 	clk;
input 	ce;
input 	reset;
output 	[15:0] sine;
output 	[15:0] cose;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("dds_v.sdo");
// synopsys translate_on

wire \clk~combout ;
wire \clk~clkctrl_outclk ;
wire \ADD_A[22]~feeder_combout ;
wire \reset~combout ;
wire \reset~clkctrl_outclk ;
wire \we~combout ;
wire \ADD_A[21]~feeder_combout ;
wire \ADD_A[20]~feeder_combout ;
wire \ADD_A[19]~feeder_combout ;
wire \ADD_A[17]~feeder_combout ;
wire \ADD_A[14]~feeder_combout ;
wire \ADD_A[13]~feeder_combout ;
wire \ADD_A[12]~feeder_combout ;
wire \ADD_A[11]~feeder_combout ;
wire \ADD_A[9]~feeder_combout ;
wire \ADD_A[5]~feeder_combout ;
wire \ADD_A[4]~feeder_combout ;
wire \ADD_A[3]~feeder_combout ;
wire \ADD_A[2]~feeder_combout ;
wire \ADD_A[1]~feeder_combout ;
wire \ADD_A[0]~feeder_combout ;
wire \Add0~449_sumout ;
wire \ce~combout ;
wire \Add0~450 ;
wire \Add0~453_sumout ;
wire \Add0~454 ;
wire \Add0~457_sumout ;
wire \Add0~458 ;
wire \Add0~461_sumout ;
wire \Add0~462 ;
wire \Add0~465_sumout ;
wire \Add0~466 ;
wire \Add0~469_sumout ;
wire \Add0~470 ;
wire \Add0~473_sumout ;
wire \Add0~474 ;
wire \Add0~477_sumout ;
wire \Add0~478 ;
wire \Add0~481_sumout ;
wire \Add0~482 ;
wire \Add0~485_sumout ;
wire \Add0~486 ;
wire \Add0~489_sumout ;
wire \Add0~490 ;
wire \Add0~493_sumout ;
wire \Add0~494 ;
wire \Add0~497_sumout ;
wire \Add0~498 ;
wire \Add0~501_sumout ;
wire \Add0~502 ;
wire \Add0~505_sumout ;
wire \Add0~506 ;
wire \Add0~509_sumout ;
wire \Add0~510 ;
wire \Add0~513_sumout ;
wire \Add0~514 ;
wire \Add0~517_sumout ;
wire \Add0~518 ;
wire \Add0~521_sumout ;
wire \Add0~522 ;
wire \Add0~525_sumout ;
wire \Add0~526 ;
wire \Add0~529_sumout ;
wire \Add0~530 ;
wire \Add0~533_sumout ;
wire \Add0~534 ;
wire \Add0~537_sumout ;
wire \ADD_A[23]~feeder_combout ;
wire \Add0~538 ;
wire \Add0~541_sumout ;
wire \ADD_A[24]~feeder_combout ;
wire \Add0~542 ;
wire \Add0~545_sumout ;
wire \Add0~546 ;
wire \Add0~549_sumout ;
wire \Add0~550 ;
wire \Add0~553_sumout ;
wire \Add0~554 ;
wire \Add0~557_sumout ;
wire \ADD_A[28]~feeder_combout ;
wire \Add0~558 ;
wire \Add0~561_sumout ;
wire \Add0~562 ;
wire \Add0~565_sumout ;
wire \Add0~566 ;
wire \Add0~569_sumout ;
wire \ADD_A[31]~feeder_combout ;
wire \Add0~570 ;
wire \Add0~573_sumout ;
wire \sine_DR[0]~feeder_combout ;
wire \sine_DR[1]~feeder_combout ;
wire \sine_DR[2]~feeder_combout ;
wire \sine_DR[5]~feeder_combout ;
wire \sine_DR[6]~feeder_combout ;
wire \sine_DR[7]~feeder_combout ;
wire \sine_DR[8]~feeder_combout ;
wire \sine_DR[9]~feeder_combout ;
wire \sine_DR[10]~feeder_combout ;
wire \sine_DR[11]~feeder_combout ;
wire \sine_DR[12]~feeder_combout ;
wire \sine_DR[14]~feeder_combout ;
wire \sine_DR[15]~feeder_combout ;
wire \cose_DR[4]~feeder_combout ;
wire \cose_DR[5]~feeder_combout ;
wire \cose_DR[6]~feeder_combout ;
wire \cose_DR[7]~feeder_combout ;
wire \cose_DR[9]~feeder_combout ;
wire \cose_DR[10]~feeder_combout ;
wire \cose_DR[11]~feeder_combout ;
wire \cose_DR[12]~feeder_combout ;
wire \cose_DR[14]~feeder_combout ;
wire [15:0] \sine1|altsyncram_component|auto_generated|q_a ;
wire [15:0] \cose1|altsyncram_component|auto_generated|q_a ;
wire [31:0] ADD_A;
wire [31:0] ADD_B;
wire [15:0] cose_DR;
wire [31:0] \data~combout ;
wire [15:0] sine_DR;

wire [3:0] \sine1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ;
wire [3:0] \sine1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ;
wire [3:0] \sine1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ;
wire [3:0] \sine1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ;
wire [3:0] \cose1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ;
wire [3:0] \cose1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ;
wire [3:0] \cose1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ;
wire [3:0] \cose1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ;

assign \sine1|altsyncram_component|auto_generated|q_a [0] = \sine1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0];
assign \sine1|altsyncram_component|auto_generated|q_a [1] = \sine1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1];
assign \sine1|altsyncram_component|auto_generated|q_a [2] = \sine1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2];
assign \sine1|altsyncram_component|auto_generated|q_a [3] = \sine1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3];

assign \sine1|altsyncram_component|auto_generated|q_a [4] = \sine1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0];
assign \sine1|altsyncram_component|auto_generated|q_a [5] = \sine1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [1];
assign \sine1|altsyncram_component|auto_generated|q_a [6] = \sine1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [2];
assign \sine1|altsyncram_component|auto_generated|q_a [7] = \sine1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [3];

assign \sine1|altsyncram_component|auto_generated|q_a [8] = \sine1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0];
assign \sine1|altsyncram_component|auto_generated|q_a [9] = \sine1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [1];
assign \sine1|altsyncram_component|auto_generated|q_a [10] = \sine1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [2];
assign \sine1|altsyncram_component|auto_generated|q_a [11] = \sine1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [3];

assign \sine1|altsyncram_component|auto_generated|q_a [12] = \sine1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0];
assign \sine1|altsyncram_component|auto_generated|q_a [13] = \sine1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [1];
assign \sine1|altsyncram_component|auto_generated|q_a [14] = \sine1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [2];
assign \sine1|altsyncram_component|auto_generated|q_a [15] = \sine1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [3];

assign \cose1|altsyncram_component|auto_generated|q_a [0] = \cose1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0];
assign \cose1|altsyncram_component|auto_generated|q_a [1] = \cose1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1];
assign \cose1|altsyncram_component|auto_generated|q_a [2] = \cose1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2];
assign \cose1|altsyncram_component|auto_generated|q_a [3] = \cose1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3];

assign \cose1|altsyncram_component|auto_generated|q_a [4] = \cose1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0];
assign \cose1|altsyncram_component|auto_generated|q_a [5] = \cose1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [1];
assign \cose1|altsyncram_component|auto_generated|q_a [6] = \cose1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [2];
assign \cose1|altsyncram_component|auto_generated|q_a [7] = \cose1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [3];

assign \cose1|altsyncram_component|auto_generated|q_a [8] = \cose1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0];
assign \cose1|altsyncram_component|auto_generated|q_a [9] = \cose1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [1];
assign \cose1|altsyncram_component|auto_generated|q_a [10] = \cose1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [2];
assign \cose1|altsyncram_component|auto_generated|q_a [11] = \cose1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [3];

assign \cose1|altsyncram_component|auto_generated|q_a [12] = \cose1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0];
assign \cose1|altsyncram_component|auto_generated|q_a [13] = \cose1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [1];
assign \cose1|altsyncram_component|auto_generated|q_a [14] = \cose1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [2];
assign \cose1|altsyncram_component|auto_generated|q_a [15] = \cose1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [3];

// atom is at PIN_U26
arriagx_io \clk~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\clk~combout ),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(clk));
// synopsys translate_off
defparam \clk~I .ddio_mode = "none";
defparam \clk~I .ddioinclk_input = "negated_inclk";
defparam \clk~I .dqs_delay_buffer_mode = "none";
defparam \clk~I .dqs_out_mode = "none";
defparam \clk~I .inclk_input = "normal";
defparam \clk~I .input_async_reset = "none";
defparam \clk~I .input_power_up = "low";
defparam \clk~I .input_register_mode = "none";
defparam \clk~I .input_sync_reset = "none";
defparam \clk~I .oe_async_reset = "none";
defparam \clk~I .oe_power_up = "low";
defparam \clk~I .oe_register_mode = "none";
defparam \clk~I .oe_sync_reset = "none";
defparam \clk~I .operation_mode = "input";
defparam \clk~I .output_async_reset = "none";
defparam \clk~I .output_power_up = "low";
defparam \clk~I .output_register_mode = "none";
defparam \clk~I .output_sync_reset = "none";
defparam \clk~I .sim_dqs_delay_increment = 0;
defparam \clk~I .sim_dqs_intrinsic_delay = 0;
defparam \clk~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at CLKCTRL_G3
arriagx_clkctrl \clk~clkctrl (
	.ena(vcc),
	.inclk({gnd,gnd,gnd,\clk~combout }),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\clk~clkctrl_outclk ));
// synopsys translate_off
defparam \clk~clkctrl .clock_type = "global clock";
// synopsys translate_on

// atom is at PIN_AG17
arriagx_io \data[22]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [22]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data[22]));
// synopsys translate_off
defparam \data[22]~I .ddio_mode = "none";
defparam \data[22]~I .ddioinclk_input = "negated_inclk";
defparam \data[22]~I .dqs_delay_buffer_mode = "none";
defparam \data[22]~I .dqs_out_mode = "none";
defparam \data[22]~I .inclk_input = "normal";
defparam \data[22]~I .input_async_reset = "none";
defparam \data[22]~I .input_power_up = "low";
defparam \data[22]~I .input_register_mode = "none";
defparam \data[22]~I .input_sync_reset = "none";
defparam \data[22]~I .oe_async_reset = "none";
defparam \data[22]~I .oe_power_up = "low";
defparam \data[22]~I .oe_register_mode = "none";
defparam \data[22]~I .oe_sync_reset = "none";
defparam \data[22]~I .operation_mode = "input";
defparam \data[22]~I .output_async_reset = "none";
defparam \data[22]~I .output_power_up = "low";
defparam \data[22]~I .output_register_mode = "none";
defparam \data[22]~I .output_sync_reset = "none";
defparam \data[22]~I .sim_dqs_delay_increment = 0;
defparam \data[22]~I .sim_dqs_intrinsic_delay = 0;
defparam \data[22]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at LCCOMB_X44_Y19_N26
arriagx_lcell_comb \ADD_A[22]~feeder (
// Equation(s):
// \ADD_A[22]~feeder_combout  = \data~combout [22]

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.datae(vcc),
	.dataf(!\data~combout [22]),
	.datag(vcc),
	.cin(gnd),
	.sharein(gnd),
	.combout(\ADD_A[22]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \ADD_A[22]~feeder .extended_lut = "off";
defparam \ADD_A[22]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \ADD_A[22]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at PIN_T25
arriagx_io \reset~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\reset~combout ),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(reset));
// synopsys translate_off
defparam \reset~I .ddio_mode = "none";
defparam \reset~I .ddioinclk_input = "negated_inclk";
defparam \reset~I .dqs_delay_buffer_mode = "none";
defparam \reset~I .dqs_out_mode = "none";
defparam \reset~I .inclk_input = "normal";
defparam \reset~I .input_async_reset = "none";
defparam \reset~I .input_power_up = "low";
defparam \reset~I .input_register_mode = "none";
defparam \reset~I .input_sync_reset = "none";
defparam \reset~I .oe_async_reset = "none";
defparam \reset~I .oe_power_up = "low";
defparam \reset~I .oe_register_mode = "none";
defparam \reset~I .oe_sync_reset = "none";
defparam \reset~I .operation_mode = "input";
defparam \reset~I .output_async_reset = "none";
defparam \reset~I .output_power_up = "low";
defparam \reset~I .output_register_mode = "none";
defparam \reset~I .output_sync_reset = "none";
defparam \reset~I .sim_dqs_delay_increment = 0;
defparam \reset~I .sim_dqs_intrinsic_delay = 0;
defparam \reset~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at CLKCTRL_G1
arriagx_clkctrl \reset~clkctrl (
	.ena(vcc),
	.inclk({gnd,gnd,gnd,\reset~combout }),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\reset~clkctrl_outclk ));
// synopsys translate_off
defparam \reset~clkctrl .clock_type = "global clock";
// synopsys translate_on

// atom is at PIN_AF14
arriagx_io \we~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),