dds_fast.vo

数字信号源

defparam \data[6]~I .sim_dqs_intrinsic_delay = 0;
defparam \data[6]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at LCFF_X46_Y19_N23
arriagx_lcell_ff \ADD_A[6] (
	.clk(\clk~clkctrl_outclk ),
	.datain(gnd),
	.adatasdata(\data~combout [6]),
	.aclr(\reset~clkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(\we~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(ADD_A[6]));

// atom is at PIN_G14
arriagx_io \data[5]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [5]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data[5]));
// synopsys translate_off
defparam \data[5]~I .ddio_mode = "none";
defparam \data[5]~I .ddioinclk_input = "negated_inclk";
defparam \data[5]~I .dqs_delay_buffer_mode = "none";
defparam \data[5]~I .dqs_out_mode = "none";
defparam \data[5]~I .inclk_input = "normal";
defparam \data[5]~I .input_async_reset = "none";
defparam \data[5]~I .input_power_up = "low";
defparam \data[5]~I .input_register_mode = "none";
defparam \data[5]~I .input_sync_reset = "none";
defparam \data[5]~I .oe_async_reset = "none";
defparam \data[5]~I .oe_power_up = "low";
defparam \data[5]~I .oe_register_mode = "none";
defparam \data[5]~I .oe_sync_reset = "none";
defparam \data[5]~I .operation_mode = "input";
defparam \data[5]~I .output_async_reset = "none";
defparam \data[5]~I .output_power_up = "low";
defparam \data[5]~I .output_register_mode = "none";
defparam \data[5]~I .output_sync_reset = "none";
defparam \data[5]~I .sim_dqs_delay_increment = 0;
defparam \data[5]~I .sim_dqs_intrinsic_delay = 0;
defparam \data[5]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at LCCOMB_X46_Y19_N30
arriagx_lcell_comb \ADD_A[5]~feeder (
// Equation(s):
// \ADD_A[5]~feeder_combout  = \data~combout [5]

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.datae(vcc),
	.dataf(!\data~combout [5]),
	.datag(vcc),
	.cin(gnd),
	.sharein(gnd),
	.combout(\ADD_A[5]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \ADD_A[5]~feeder .extended_lut = "off";
defparam \ADD_A[5]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \ADD_A[5]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at LCFF_X46_Y19_N31
arriagx_lcell_ff \ADD_A[5] (
	.clk(\clk~clkctrl_outclk ),
	.datain(\ADD_A[5]~feeder_combout ),
	.adatasdata(gnd),
	.aclr(\reset~clkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\we~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(ADD_A[5]));

// atom is at PIN_AC27
arriagx_io \data[4]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [4]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data[4]));
// synopsys translate_off
defparam \data[4]~I .ddio_mode = "none";
defparam \data[4]~I .ddioinclk_input = "negated_inclk";
defparam \data[4]~I .dqs_delay_buffer_mode = "none";
defparam \data[4]~I .dqs_out_mode = "none";
defparam \data[4]~I .inclk_input = "normal";
defparam \data[4]~I .input_async_reset = "none";
defparam \data[4]~I .input_power_up = "low";
defparam \data[4]~I .input_register_mode = "none";
defparam \data[4]~I .input_sync_reset = "none";
defparam \data[4]~I .oe_async_reset = "none";
defparam \data[4]~I .oe_power_up = "low";
defparam \data[4]~I .oe_register_mode = "none";
defparam \data[4]~I .oe_sync_reset = "none";
defparam \data[4]~I .operation_mode = "input";
defparam \data[4]~I .output_async_reset = "none";
defparam \data[4]~I .output_power_up = "low";
defparam \data[4]~I .output_register_mode = "none";
defparam \data[4]~I .output_sync_reset = "none";
defparam \data[4]~I .sim_dqs_delay_increment = 0;
defparam \data[4]~I .sim_dqs_intrinsic_delay = 0;
defparam \data[4]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at LCCOMB_X46_Y19_N28
arriagx_lcell_comb \ADD_A[4]~feeder (
// Equation(s):
// \ADD_A[4]~feeder_combout  = \data~combout [4]

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.datae(vcc),
	.dataf(!\data~combout [4]),
	.datag(vcc),
	.cin(gnd),
	.sharein(gnd),
	.combout(\ADD_A[4]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \ADD_A[4]~feeder .extended_lut = "off";
defparam \ADD_A[4]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \ADD_A[4]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at LCFF_X46_Y19_N29
arriagx_lcell_ff \ADD_A[4] (
	.clk(\clk~clkctrl_outclk ),
	.datain(\ADD_A[4]~feeder_combout ),
	.adatasdata(gnd),
	.aclr(\reset~clkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\we~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(ADD_A[4]));

// atom is at PIN_AD14
arriagx_io \data[3]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [3]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data[3]));
// synopsys translate_off
defparam \data[3]~I .ddio_mode = "none";
defparam \data[3]~I .ddioinclk_input = "negated_inclk";
defparam \data[3]~I .dqs_delay_buffer_mode = "none";
defparam \data[3]~I .dqs_out_mode = "none";
defparam \data[3]~I .inclk_input = "normal";
defparam \data[3]~I .input_async_reset = "none";
defparam \data[3]~I .input_power_up = "low";
defparam \data[3]~I .input_register_mode = "none";
defparam \data[3]~I .input_sync_reset = "none";
defparam \data[3]~I .oe_async_reset = "none";
defparam \data[3]~I .oe_power_up = "low";
defparam \data[3]~I .oe_register_mode = "none";
defparam \data[3]~I .oe_sync_reset = "none";
defparam \data[3]~I .operation_mode = "input";
defparam \data[3]~I .output_async_reset = "none";
defparam \data[3]~I .output_power_up = "low";
defparam \data[3]~I .output_register_mode = "none";
defparam \data[3]~I .output_sync_reset = "none";
defparam \data[3]~I .sim_dqs_delay_increment = 0;
defparam \data[3]~I .sim_dqs_intrinsic_delay = 0;
defparam \data[3]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at LCCOMB_X46_Y19_N12
arriagx_lcell_comb \ADD_A[3]~feeder (
// Equation(s):
// \ADD_A[3]~feeder_combout  = \data~combout [3]

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.datae(vcc),
	.dataf(!\data~combout [3]),
	.datag(vcc),
	.cin(gnd),
	.sharein(gnd),
	.combout(\ADD_A[3]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \ADD_A[3]~feeder .extended_lut = "off";
defparam \ADD_A[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \ADD_A[3]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at LCFF_X46_Y19_N13
arriagx_lcell_ff \ADD_A[3] (
	.clk(\clk~clkctrl_outclk ),
	.datain(\ADD_A[3]~feeder_combout ),
	.adatasdata(gnd),
	.aclr(\reset~clkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\we~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(ADD_A[3]));

// atom is at PIN_AA26
arriagx_io \data[2]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [2]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data[2]));
// synopsys translate_off
defparam \data[2]~I .ddio_mode = "none";
defparam \data[2]~I .ddioinclk_input = "negated_inclk";
defparam \data[2]~I .dqs_delay_buffer_mode = "none";
defparam \data[2]~I .dqs_out_mode = "none";
defparam \data[2]~I .inclk_input = "normal";
defparam \data[2]~I .input_async_reset = "none";
defparam \data[2]~I .input_power_up = "low";
defparam \data[2]~I .input_register_mode = "none";
defparam \data[2]~I .input_sync_reset = "none";
defparam \data[2]~I .oe_async_reset = "none";
defparam \data[2]~I .oe_power_up = "low";
defparam \data[2]~I .oe_register_mode = "none";
defparam \data[2]~I .oe_sync_reset = "none";
defparam \data[2]~I .operation_mode = "input";
defparam \data[2]~I .output_async_reset = "none";
defparam \data[2]~I .output_power_up = "low";
defparam \data[2]~I .output_register_mode = "none";
defparam \data[2]~I .output_sync_reset = "none";
defparam \data[2]~I .sim_dqs_delay_increment = 0;
defparam \data[2]~I .sim_dqs_intrinsic_delay = 0;
defparam \data[2]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at LCCOMB_X46_Y19_N14
arriagx_lcell_comb \ADD_A[2]~feeder (
// Equation(s):
// \ADD_A[2]~feeder_combout  = \data~combout [2]

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.datae(vcc),
	.dataf(!\data~combout [2]),
	.datag(vcc),
	.cin(gnd),
	.sharein(gnd),
	.combout(\ADD_A[2]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \ADD_A[2]~feeder .extended_lut = "off";
defparam \ADD_A[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \ADD_A[2]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at LCFF_X46_Y19_N15
arriagx_lcell_ff \ADD_A[2] (
	.clk(\clk~clkctrl_outclk ),
	.datain(\ADD_A[2]~feeder_combout ),
	.adatasdata(gnd),
	.aclr(\reset~clkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\we~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(ADD_A[2]));

// atom is at PIN_V23
arriagx_io \data[1]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [1]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data[1]));
// synopsys translate_off
defparam \data[1]~I .ddio_mode = "none";
defparam \data[1]~I .ddioinclk_input = "negated_inclk";
defparam \data[1]~I .dqs_delay_buffer_mode = "none";
defparam \data[1]~I .dqs_out_mode = "none";
defparam \data[1]~I .inclk_input = "normal";
defparam \data[1]~I .input_async_reset = "none";
defparam \data[1]~I .input_power_up = "low";
defparam \data[1]~I .input_register_mode = "none";
defparam \data[1]~I .input_sync_reset = "none";
defparam \data[1]~I .oe_async_reset = "none";
defparam \data[1]~I .oe_power_up = "low";
defparam \data[1]~I .oe_register_mode = "none";
defparam \data[1]~I .oe_sync_reset = "none";
defparam \data[1]~I .operation_mode = "input";
defparam \data[1]~I .output_async_reset = "none";
defparam \data[1]~I .output_power_up = "low";
defparam \data[1]~I .output_register_mode = "none";
defparam \data[1]~I .output_sync_reset = "none";
defparam \data[1]~I .sim_dqs_delay_increment = 0;
defparam \data[1]~I .sim_dqs_intrinsic_delay = 0;
defparam \data[1]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at LCCOMB_X46_Y19_N10
arriagx_lcell_comb \ADD_A[1]~feeder (
// Equation(s):
// \ADD_A[1