dds_fast.vo

数字信号源

arriagx_lcell_ff \ADD_A[12] (
	.clk(\clk~clkctrl_outclk ),
	.datain(\ADD_A[12]~feeder_combout ),
	.adatasdata(gnd),
	.aclr(\reset~clkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\we~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(ADD_A[12]));

// atom is at PIN_V22
arriagx_io \data[11]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [11]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data[11]));
// synopsys translate_off
defparam \data[11]~I .ddio_mode = "none";
defparam \data[11]~I .ddioinclk_input = "negated_inclk";
defparam \data[11]~I .dqs_delay_buffer_mode = "none";
defparam \data[11]~I .dqs_out_mode = "none";
defparam \data[11]~I .inclk_input = "normal";
defparam \data[11]~I .input_async_reset = "none";
defparam \data[11]~I .input_power_up = "low";
defparam \data[11]~I .input_register_mode = "none";
defparam \data[11]~I .input_sync_reset = "none";
defparam \data[11]~I .oe_async_reset = "none";
defparam \data[11]~I .oe_power_up = "low";
defparam \data[11]~I .oe_register_mode = "none";
defparam \data[11]~I .oe_sync_reset = "none";
defparam \data[11]~I .operation_mode = "input";
defparam \data[11]~I .output_async_reset = "none";
defparam \data[11]~I .output_power_up = "low";
defparam \data[11]~I .output_register_mode = "none";
defparam \data[11]~I .output_sync_reset = "none";
defparam \data[11]~I .sim_dqs_delay_increment = 0;
defparam \data[11]~I .sim_dqs_intrinsic_delay = 0;
defparam \data[11]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at LCCOMB_X44_Y19_N14
arriagx_lcell_comb \ADD_A[11]~feeder (
// Equation(s):
// \ADD_A[11]~feeder_combout  = \data~combout [11]

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.datae(vcc),
	.dataf(!\data~combout [11]),
	.datag(vcc),
	.cin(gnd),
	.sharein(gnd),
	.combout(\ADD_A[11]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \ADD_A[11]~feeder .extended_lut = "off";
defparam \ADD_A[11]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \ADD_A[11]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at LCFF_X44_Y19_N15
arriagx_lcell_ff \ADD_A[11] (
	.clk(\clk~clkctrl_outclk ),
	.datain(\ADD_A[11]~feeder_combout ),
	.adatasdata(gnd),
	.aclr(\reset~clkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\we~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(ADD_A[11]));

// atom is at PIN_Y26
arriagx_io \data[10]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [10]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data[10]));
// synopsys translate_off
defparam \data[10]~I .ddio_mode = "none";
defparam \data[10]~I .ddioinclk_input = "negated_inclk";
defparam \data[10]~I .dqs_delay_buffer_mode = "none";
defparam \data[10]~I .dqs_out_mode = "none";
defparam \data[10]~I .inclk_input = "normal";
defparam \data[10]~I .input_async_reset = "none";
defparam \data[10]~I .input_power_up = "low";
defparam \data[10]~I .input_register_mode = "none";
defparam \data[10]~I .input_sync_reset = "none";
defparam \data[10]~I .oe_async_reset = "none";
defparam \data[10]~I .oe_power_up = "low";
defparam \data[10]~I .oe_register_mode = "none";
defparam \data[10]~I .oe_sync_reset = "none";
defparam \data[10]~I .operation_mode = "input";
defparam \data[10]~I .output_async_reset = "none";
defparam \data[10]~I .output_power_up = "low";
defparam \data[10]~I .output_register_mode = "none";
defparam \data[10]~I .output_sync_reset = "none";
defparam \data[10]~I .sim_dqs_delay_increment = 0;
defparam \data[10]~I .sim_dqs_intrinsic_delay = 0;
defparam \data[10]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at LCFF_X44_Y19_N13
arriagx_lcell_ff \ADD_A[10] (
	.clk(\clk~clkctrl_outclk ),
	.datain(gnd),
	.adatasdata(\data~combout [10]),
	.aclr(\reset~clkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(\we~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(ADD_A[10]));

// atom is at PIN_AF15
arriagx_io \data[9]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [9]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data[9]));
// synopsys translate_off
defparam \data[9]~I .ddio_mode = "none";
defparam \data[9]~I .ddioinclk_input = "negated_inclk";
defparam \data[9]~I .dqs_delay_buffer_mode = "none";
defparam \data[9]~I .dqs_out_mode = "none";
defparam \data[9]~I .inclk_input = "normal";
defparam \data[9]~I .input_async_reset = "none";
defparam \data[9]~I .input_power_up = "low";
defparam \data[9]~I .input_register_mode = "none";
defparam \data[9]~I .input_sync_reset = "none";
defparam \data[9]~I .oe_async_reset = "none";
defparam \data[9]~I .oe_power_up = "low";
defparam \data[9]~I .oe_register_mode = "none";
defparam \data[9]~I .oe_sync_reset = "none";
defparam \data[9]~I .operation_mode = "input";
defparam \data[9]~I .output_async_reset = "none";
defparam \data[9]~I .output_power_up = "low";
defparam \data[9]~I .output_register_mode = "none";
defparam \data[9]~I .output_sync_reset = "none";
defparam \data[9]~I .sim_dqs_delay_increment = 0;
defparam \data[9]~I .sim_dqs_intrinsic_delay = 0;
defparam \data[9]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at LCCOMB_X44_Y19_N2
arriagx_lcell_comb \ADD_A[9]~feeder (
// Equation(s):
// \ADD_A[9]~feeder_combout  = \data~combout [9]

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.datae(vcc),
	.dataf(!\data~combout [9]),
	.datag(vcc),
	.cin(gnd),
	.sharein(gnd),
	.combout(\ADD_A[9]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \ADD_A[9]~feeder .extended_lut = "off";
defparam \ADD_A[9]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \ADD_A[9]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at LCFF_X44_Y19_N3
arriagx_lcell_ff \ADD_A[9] (
	.clk(\clk~clkctrl_outclk ),
	.datain(\ADD_A[9]~feeder_combout ),
	.adatasdata(gnd),
	.aclr(\reset~clkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\we~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(ADD_A[9]));

// atom is at PIN_AH16
arriagx_io \data[8]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [8]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data[8]));
// synopsys translate_off
defparam \data[8]~I .ddio_mode = "none";
defparam \data[8]~I .ddioinclk_input = "negated_inclk";
defparam \data[8]~I .dqs_delay_buffer_mode = "none";
defparam \data[8]~I .dqs_out_mode = "none";
defparam \data[8]~I .inclk_input = "normal";
defparam \data[8]~I .input_async_reset = "none";
defparam \data[8]~I .input_power_up = "low";
defparam \data[8]~I .input_register_mode = "none";
defparam \data[8]~I .input_sync_reset = "none";
defparam \data[8]~I .oe_async_reset = "none";
defparam \data[8]~I .oe_power_up = "low";
defparam \data[8]~I .oe_register_mode = "none";
defparam \data[8]~I .oe_sync_reset = "none";
defparam \data[8]~I .operation_mode = "input";
defparam \data[8]~I .output_async_reset = "none";
defparam \data[8]~I .output_power_up = "low";
defparam \data[8]~I .output_register_mode = "none";
defparam \data[8]~I .output_sync_reset = "none";
defparam \data[8]~I .sim_dqs_delay_increment = 0;
defparam \data[8]~I .sim_dqs_intrinsic_delay = 0;
defparam \data[8]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at LCFF_X44_Y19_N1
arriagx_lcell_ff \ADD_A[8] (
	.clk(\clk~clkctrl_outclk ),
	.datain(gnd),
	.adatasdata(\data~combout [8]),
	.aclr(\reset~clkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(\we~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(ADD_A[8]));

// atom is at PIN_AF13
arriagx_io \data[7]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [7]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data[7]));
// synopsys translate_off
defparam \data[7]~I .ddio_mode = "none";
defparam \data[7]~I .ddioinclk_input = "negated_inclk";
defparam \data[7]~I .dqs_delay_buffer_mode = "none";
defparam \data[7]~I .dqs_out_mode = "none";
defparam \data[7]~I .inclk_input = "normal";
defparam \data[7]~I .input_async_reset = "none";
defparam \data[7]~I .input_power_up = "low";
defparam \data[7]~I .input_register_mode = "none";
defparam \data[7]~I .input_sync_reset = "none";
defparam \data[7]~I .oe_async_reset = "none";
defparam \data[7]~I .oe_power_up = "low";
defparam \data[7]~I .oe_register_mode = "none";
defparam \data[7]~I .oe_sync_reset = "none";
defparam \data[7]~I .operation_mode = "input";
defparam \data[7]~I .output_async_reset = "none";
defparam \data[7]~I .output_power_up = "low";
defparam \data[7]~I .output_register_mode = "none";
defparam \data[7]~I .output_sync_reset = "none";
defparam \data[7]~I .sim_dqs_delay_increment = 0;
defparam \data[7]~I .sim_dqs_intrinsic_delay = 0;
defparam \data[7]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at LCFF_X46_Y19_N21
arriagx_lcell_ff \ADD_A[7] (
	.clk(\clk~clkctrl_outclk ),
	.datain(gnd),
	.adatasdata(\data~combout [7]),
	.aclr(\reset~clkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(\we~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(ADD_A[7]));

// atom is at PIN_F14
arriagx_io \data[6]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [6]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data[6]));
// synopsys translate_off
defparam \data[6]~I .ddio_mode = "none";
defparam \data[6]~I .ddioinclk_input = "negated_inclk";
defparam \data[6]~I .dqs_delay_buffer_mode = "none";
defparam \data[6]~I .dqs_out_mode = "none";
defparam \data[6]~I .inclk_input = "normal";
defparam \data[6]~I .input_async_reset = "none";
defparam \data[6]~I .input_power_up = "low";
defparam \data[6]~I .input_register_mode = "none";
defparam \data[6]~I .input_sync_reset = "none";
defparam \data[6]~I .oe_async_reset = "none";
defparam \data[6]~I .oe_power_up = "low";
defparam \data[6]~I .oe_register_mode = "none";
defparam \data[6]~I .oe_sync_reset = "none";
defparam \data[6]~I .operation_mode = "input";
defparam \data[6]~I .output_async_reset = "none";
defparam \data[6]~I .output_power_up = "low";
defparam \data[6]~I .output_register_mode = "none";
defparam \data[6]~I .output_sync_reset = "none";
defparam \data[6]~I .sim_dqs_delay_increment = 0;