dds_fast.vo

数字信号源

defparam \data[17]~I .operation_mode = "input";
defparam \data[17]~I .output_async_reset = "none";
defparam \data[17]~I .output_power_up = "low";
defparam \data[17]~I .output_register_mode = "none";
defparam \data[17]~I .output_sync_reset = "none";
defparam \data[17]~I .sim_dqs_delay_increment = 0;
defparam \data[17]~I .sim_dqs_intrinsic_delay = 0;
defparam \data[17]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at LCCOMB_X44_Y19_N18
arriagx_lcell_comb \ADD_A[17]~feeder (
// Equation(s):
// \ADD_A[17]~feeder_combout  = \data~combout [17]

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.datae(vcc),
	.dataf(!\data~combout [17]),
	.datag(vcc),
	.cin(gnd),
	.sharein(gnd),
	.combout(\ADD_A[17]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \ADD_A[17]~feeder .extended_lut = "off";
defparam \ADD_A[17]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \ADD_A[17]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at LCFF_X44_Y19_N19
arriagx_lcell_ff \ADD_A[17] (
	.clk(\clk~clkctrl_outclk ),
	.datain(\ADD_A[17]~feeder_combout ),
	.adatasdata(gnd),
	.aclr(\reset~clkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\we~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(ADD_A[17]));

// atom is at PIN_G15
arriagx_io \data[16]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [16]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data[16]));
// synopsys translate_off
defparam \data[16]~I .ddio_mode = "none";
defparam \data[16]~I .ddioinclk_input = "negated_inclk";
defparam \data[16]~I .dqs_delay_buffer_mode = "none";
defparam \data[16]~I .dqs_out_mode = "none";
defparam \data[16]~I .inclk_input = "normal";
defparam \data[16]~I .input_async_reset = "none";
defparam \data[16]~I .input_power_up = "low";
defparam \data[16]~I .input_register_mode = "none";
defparam \data[16]~I .input_sync_reset = "none";
defparam \data[16]~I .oe_async_reset = "none";
defparam \data[16]~I .oe_power_up = "low";
defparam \data[16]~I .oe_register_mode = "none";
defparam \data[16]~I .oe_sync_reset = "none";
defparam \data[16]~I .operation_mode = "input";
defparam \data[16]~I .output_async_reset = "none";
defparam \data[16]~I .output_power_up = "low";
defparam \data[16]~I .output_register_mode = "none";
defparam \data[16]~I .output_sync_reset = "none";
defparam \data[16]~I .sim_dqs_delay_increment = 0;
defparam \data[16]~I .sim_dqs_intrinsic_delay = 0;
defparam \data[16]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at LCFF_X44_Y19_N17
arriagx_lcell_ff \ADD_A[16] (
	.clk(\clk~clkctrl_outclk ),
	.datain(gnd),
	.adatasdata(\data~combout [16]),
	.aclr(\reset~clkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(\we~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(ADD_A[16]));

// atom is at PIN_AB28
arriagx_io \data[15]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [15]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data[15]));
// synopsys translate_off
defparam \data[15]~I .ddio_mode = "none";
defparam \data[15]~I .ddioinclk_input = "negated_inclk";
defparam \data[15]~I .dqs_delay_buffer_mode = "none";
defparam \data[15]~I .dqs_out_mode = "none";
defparam \data[15]~I .inclk_input = "normal";
defparam \data[15]~I .input_async_reset = "none";
defparam \data[15]~I .input_power_up = "low";
defparam \data[15]~I .input_register_mode = "none";
defparam \data[15]~I .input_sync_reset = "none";
defparam \data[15]~I .oe_async_reset = "none";
defparam \data[15]~I .oe_power_up = "low";
defparam \data[15]~I .oe_register_mode = "none";
defparam \data[15]~I .oe_sync_reset = "none";
defparam \data[15]~I .operation_mode = "input";
defparam \data[15]~I .output_async_reset = "none";
defparam \data[15]~I .output_power_up = "low";
defparam \data[15]~I .output_register_mode = "none";
defparam \data[15]~I .output_sync_reset = "none";
defparam \data[15]~I .sim_dqs_delay_increment = 0;
defparam \data[15]~I .sim_dqs_intrinsic_delay = 0;
defparam \data[15]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at LCFF_X44_Y19_N29
arriagx_lcell_ff \ADD_A[15] (
	.clk(\clk~clkctrl_outclk ),
	.datain(gnd),
	.adatasdata(\data~combout [15]),
	.aclr(\reset~clkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(\we~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(ADD_A[15]));

// atom is at PIN_AE15
arriagx_io \data[14]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [14]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data[14]));
// synopsys translate_off
defparam \data[14]~I .ddio_mode = "none";
defparam \data[14]~I .ddioinclk_input = "negated_inclk";
defparam \data[14]~I .dqs_delay_buffer_mode = "none";
defparam \data[14]~I .dqs_out_mode = "none";
defparam \data[14]~I .inclk_input = "normal";
defparam \data[14]~I .input_async_reset = "none";
defparam \data[14]~I .input_power_up = "low";
defparam \data[14]~I .input_register_mode = "none";
defparam \data[14]~I .input_sync_reset = "none";
defparam \data[14]~I .oe_async_reset = "none";
defparam \data[14]~I .oe_power_up = "low";
defparam \data[14]~I .oe_register_mode = "none";
defparam \data[14]~I .oe_sync_reset = "none";
defparam \data[14]~I .operation_mode = "input";
defparam \data[14]~I .output_async_reset = "none";
defparam \data[14]~I .output_power_up = "low";
defparam \data[14]~I .output_register_mode = "none";
defparam \data[14]~I .output_sync_reset = "none";
defparam \data[14]~I .sim_dqs_delay_increment = 0;
defparam \data[14]~I .sim_dqs_intrinsic_delay = 0;
defparam \data[14]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at LCCOMB_X44_Y19_N30
arriagx_lcell_comb \ADD_A[14]~feeder (
// Equation(s):
// \ADD_A[14]~feeder_combout  = \data~combout [14]

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.datae(vcc),
	.dataf(!\data~combout [14]),
	.datag(vcc),
	.cin(gnd),
	.sharein(gnd),
	.combout(\ADD_A[14]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \ADD_A[14]~feeder .extended_lut = "off";
defparam \ADD_A[14]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \ADD_A[14]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at LCFF_X44_Y19_N31
arriagx_lcell_ff \ADD_A[14] (
	.clk(\clk~clkctrl_outclk ),
	.datain(\ADD_A[14]~feeder_combout ),
	.adatasdata(gnd),
	.aclr(\reset~clkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\we~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(ADD_A[14]));

// atom is at PIN_AA25
arriagx_io \data[13]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [13]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data[13]));
// synopsys translate_off
defparam \data[13]~I .ddio_mode = "none";
defparam \data[13]~I .ddioinclk_input = "negated_inclk";
defparam \data[13]~I .dqs_delay_buffer_mode = "none";
defparam \data[13]~I .dqs_out_mode = "none";
defparam \data[13]~I .inclk_input = "normal";
defparam \data[13]~I .input_async_reset = "none";
defparam \data[13]~I .input_power_up = "low";
defparam \data[13]~I .input_register_mode = "none";
defparam \data[13]~I .input_sync_reset = "none";
defparam \data[13]~I .oe_async_reset = "none";
defparam \data[13]~I .oe_power_up = "low";
defparam \data[13]~I .oe_register_mode = "none";
defparam \data[13]~I .oe_sync_reset = "none";
defparam \data[13]~I .operation_mode = "input";
defparam \data[13]~I .output_async_reset = "none";
defparam \data[13]~I .output_power_up = "low";
defparam \data[13]~I .output_register_mode = "none";
defparam \data[13]~I .output_sync_reset = "none";
defparam \data[13]~I .sim_dqs_delay_increment = 0;
defparam \data[13]~I .sim_dqs_intrinsic_delay = 0;
defparam \data[13]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at LCCOMB_X44_Y19_N22
arriagx_lcell_comb \ADD_A[13]~feeder (
// Equation(s):
// \ADD_A[13]~feeder_combout  = \data~combout [13]

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.datae(vcc),
	.dataf(!\data~combout [13]),
	.datag(vcc),
	.cin(gnd),
	.sharein(gnd),
	.combout(\ADD_A[13]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \ADD_A[13]~feeder .extended_lut = "off";
defparam \ADD_A[13]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \ADD_A[13]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at LCFF_X44_Y19_N23
arriagx_lcell_ff \ADD_A[13] (
	.clk(\clk~clkctrl_outclk ),
	.datain(\ADD_A[13]~feeder_combout ),
	.adatasdata(gnd),
	.aclr(\reset~clkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\we~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(ADD_A[13]));

// atom is at PIN_V26
arriagx_io \data[12]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [12]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data[12]));
// synopsys translate_off
defparam \data[12]~I .ddio_mode = "none";
defparam \data[12]~I .ddioinclk_input = "negated_inclk";
defparam \data[12]~I .dqs_delay_buffer_mode = "none";
defparam \data[12]~I .dqs_out_mode = "none";
defparam \data[12]~I .inclk_input = "normal";
defparam \data[12]~I .input_async_reset = "none";
defparam \data[12]~I .input_power_up = "low";
defparam \data[12]~I .input_register_mode = "none";
defparam \data[12]~I .input_sync_reset = "none";
defparam \data[12]~I .oe_async_reset = "none";
defparam \data[12]~I .oe_power_up = "low";
defparam \data[12]~I .oe_register_mode = "none";
defparam \data[12]~I .oe_sync_reset = "none";
defparam \data[12]~I .operation_mode = "input";
defparam \data[12]~I .output_async_reset = "none";
defparam \data[12]~I .output_power_up = "low";
defparam \data[12]~I .output_register_mode = "none";
defparam \data[12]~I .output_sync_reset = "none";
defparam \data[12]~I .sim_dqs_delay_increment = 0;
defparam \data[12]~I .sim_dqs_intrinsic_delay = 0;
defparam \data[12]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at LCCOMB_X44_Y19_N20
arriagx_lcell_comb \ADD_A[12]~feeder (
// Equation(s):
// \ADD_A[12]~feeder_combout  = \data~combout [12]

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.datae(vcc),
	.dataf(!\data~combout [12]),
	.datag(vcc),
	.cin(gnd),
	.sharein(gnd),
	.combout(\ADD_A[12]~feeder_combout ),
	.sumout(),
	.cout(),
	.shareout());
// synopsys translate_off
defparam \ADD_A[12]~feeder .extended_lut = "off";
defparam \ADD_A[12]~feeder .lut_mask = 64'h00000000FFFFFFFF;
defparam \ADD_A[12]~feeder .shared_arith = "off";
// synopsys translate_on

// atom is at LCFF_X44_Y19_N21