📄 dds_v_fast.sdo
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// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
// Device: Altera EP1AGX60DF780C6 Package FBGA780
//
//
// This SDF file should be used for ModelSim (Verilog) only
//
(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "dds")
(DATE "11/28/2008 15:54:10")
(VENDOR "Altera")
(PROGRAM "Quartus II")
(VERSION "Version 7.2 Build 151 09/26/2007 SJ Web Edition")
(DIVIDER .)
(TIMESCALE 1 ps)
(CELL
(CELLTYPE "arriagx_asynch_io")
(INSTANCE clk\~I.inst1)
(DELAY
(ABSOLUTE
(IOPATH padio combout (493:493:493) (493:493:493))
)
)
)
(CELL
(CELLTYPE "arriagx_clkctrl")
(INSTANCE clk\~clkctrl)
(DELAY
(ABSOLUTE
(PORT inclk[0] (227:227:227) (227:227:227))
)
)
)
(CELL
(CELLTYPE "arriagx_ena_reg")
(INSTANCE clk\~clkctrl.extena0_reg)
(DELAY
(ABSOLUTE
(PORT d (0:0:0) (0:0:0))
(PORT clk (0:0:0) (0:0:0))
(IOPATH (posedge clk) q (49:49:49) (49:49:49))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (15:15:15))
(HOLD d (posedge clk) (29:29:29))
)
)
(CELL
(CELLTYPE "arriagx_asynch_io")
(INSTANCE data\[22\]\~I.inst1)
(DELAY
(ABSOLUTE
(IOPATH padio combout (474:474:474) (474:474:474))
)
)
)
(CELL
(CELLTYPE "arriagx_lcell_comb")
(INSTANCE ADD_A\[22\]\~feeder)
(DELAY
(ABSOLUTE
(PORT dataf (2994:2994:2994) (2994:2994:2994))
(IOPATH dataf combout (18:18:18) (18:18:18))
)
)
)
(CELL
(CELLTYPE "arriagx_asynch_io")
(INSTANCE reset\~I.inst1)
(DELAY
(ABSOLUTE
(IOPATH padio combout (493:493:493) (493:493:493))
)
)
)
(CELL
(CELLTYPE "arriagx_clkctrl")
(INSTANCE reset\~clkctrl)
(DELAY
(ABSOLUTE
(PORT inclk[0] (227:227:227) (227:227:227))
)
)
)
(CELL
(CELLTYPE "arriagx_ena_reg")
(INSTANCE reset\~clkctrl.extena0_reg)
(DELAY
(ABSOLUTE
(PORT d (0:0:0) (0:0:0))
(PORT clk (0:0:0) (0:0:0))
(IOPATH (posedge clk) q (49:49:49) (49:49:49))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (15:15:15))
(HOLD d (posedge clk) (29:29:29))
)
)
(CELL
(CELLTYPE "arriagx_asynch_io")
(INSTANCE we\~I.inst1)
(DELAY
(ABSOLUTE
(IOPATH padio combout (444:444:444) (444:444:444))
)
)
)
(CELL
(CELLTYPE "arriagx_lcell_ff")
(INSTANCE ADD_A\[22\])
(DELAY
(ABSOLUTE
(PORT clk (1051:1051:1051) (1051:1051:1051))
(PORT datain (97:97:97) (97:97:97))
(PORT aclr (900:900:900) (900:900:900))
(PORT ena (3156:3156:3156) (3156:3156:3156))
(IOPATH (posedge clk) regout (62:62:62) (62:62:62))
(IOPATH (posedge aclr) regout (136:136:136) (136:136:136))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (47:47:47))
(SETUP ena (posedge clk) (47:47:47))
(HOLD datain (posedge clk) (75:75:75))
(HOLD ena (posedge clk) (75:75:75))
)
)
(CELL
(CELLTYPE "arriagx_asynch_io")
(INSTANCE data\[21\]\~I.inst1)
(DELAY
(ABSOLUTE
(IOPATH padio combout (444:444:444) (444:444:444))
)
)
)
(CELL
(CELLTYPE "arriagx_lcell_comb")
(INSTANCE ADD_A\[21\]\~feeder)
(DELAY
(ABSOLUTE
(PORT dataf (2979:2979:2979) (2979:2979:2979))
(IOPATH dataf combout (18:18:18) (18:18:18))
)
)
)
(CELL
(CELLTYPE "arriagx_lcell_ff")
(INSTANCE ADD_A\[21\])
(DELAY
(ABSOLUTE
(PORT clk (1051:1051:1051) (1051:1051:1051))
(PORT datain (97:97:97) (97:97:97))
(PORT aclr (900:900:900) (900:900:900))
(PORT ena (3156:3156:3156) (3156:3156:3156))
(IOPATH (posedge clk) regout (62:62:62) (62:62:62))
(IOPATH (posedge aclr) regout (136:136:136) (136:136:136))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (47:47:47))
(SETUP ena (posedge clk) (47:47:47))
(HOLD datain (posedge clk) (75:75:75))
(HOLD ena (posedge clk) (75:75:75))
)
)
(CELL
(CELLTYPE "arriagx_asynch_io")
(INSTANCE data\[20\]\~I.inst1)
(DELAY
(ABSOLUTE
(IOPATH padio combout (450:450:450) (450:450:450))
)
)
)
(CELL
(CELLTYPE "arriagx_lcell_comb")
(INSTANCE ADD_A\[20\]\~feeder)
(DELAY
(ABSOLUTE
(PORT dataf (2847:2847:2847) (2847:2847:2847))
(IOPATH dataf combout (18:18:18) (18:18:18))
)
)
)
(CELL
(CELLTYPE "arriagx_lcell_ff")
(INSTANCE ADD_A\[20\])
(DELAY
(ABSOLUTE
(PORT clk (1051:1051:1051) (1051:1051:1051))
(PORT datain (97:97:97) (97:97:97))
(PORT aclr (900:900:900) (900:900:900))
(PORT ena (3156:3156:3156) (3156:3156:3156))
(IOPATH (posedge clk) regout (62:62:62) (62:62:62))
(IOPATH (posedge aclr) regout (136:136:136) (136:136:136))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (47:47:47))
(SETUP ena (posedge clk) (47:47:47))
(HOLD datain (posedge clk) (75:75:75))
(HOLD ena (posedge clk) (75:75:75))
)
)
(CELL
(CELLTYPE "arriagx_asynch_io")
(INSTANCE data\[19\]\~I.inst1)
(DELAY
(ABSOLUTE
(IOPATH padio combout (470:470:470) (470:470:470))
)
)
)
(CELL
(CELLTYPE "arriagx_lcell_comb")
(INSTANCE ADD_A\[19\]\~feeder)
(DELAY
(ABSOLUTE
(PORT dataf (2922:2922:2922) (2922:2922:2922))
(IOPATH dataf combout (18:18:18) (18:18:18))
)
)
)
(CELL
(CELLTYPE "arriagx_lcell_ff")
(INSTANCE ADD_A\[19\])
(DELAY
(ABSOLUTE
(PORT clk (1051:1051:1051) (1051:1051:1051))
(PORT datain (97:97:97) (97:97:97))
(PORT aclr (900:900:900) (900:900:900))
(PORT ena (3156:3156:3156) (3156:3156:3156))
(IOPATH (posedge clk) regout (62:62:62) (62:62:62))
(IOPATH (posedge aclr) regout (136:136:136) (136:136:136))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (47:47:47))
(SETUP ena (posedge clk) (47:47:47))
(HOLD datain (posedge clk) (75:75:75))
(HOLD ena (posedge clk) (75:75:75))
)
)
(CELL
(CELLTYPE "arriagx_asynch_io")
(INSTANCE data\[18\]\~I.inst1)
(DELAY
(ABSOLUTE
(IOPATH padio combout (454:454:454) (454:454:454))
)
)
)
(CELL
(CELLTYPE "arriagx_lcell_ff")
(INSTANCE ADD_A\[18\])
(DELAY
(ABSOLUTE
(PORT clk (1051:1051:1051) (1051:1051:1051))
(PORT adatasdata (2803:2803:2803) (2803:2803:2803))
(PORT aclr (900:900:900) (900:900:900))
(PORT ena (3156:3156:3156) (3156:3156:3156))
(IOPATH (posedge clk) regout (62:62:62) (62:62:62))
(IOPATH (posedge aclr) regout (136:136:136) (136:136:136))
)
)
(TIMINGCHECK
(SETUP adatasdata (posedge clk) (47:47:47))
(SETUP ena (posedge clk) (47:47:47))
(HOLD adatasdata (posedge clk) (75:75:75))
(HOLD ena (posedge clk) (75:75:75))
)
)
(CELL
(CELLTYPE "arriagx_asynch_io")
(INSTANCE data\[17\]\~I.inst1)
(DELAY
(ABSOLUTE
(IOPATH padio combout (490:490:490) (490:490:490))
)
)
)
(CELL
(CELLTYPE "arriagx_lcell_comb")
(INSTANCE ADD_A\[17\]\~feeder)
(DELAY
(ABSOLUTE
(PORT dataf (2900:2900:2900) (2900:2900:2900))
(IOPATH dataf combout (18:18:18) (18:18:18))
)
)
)
(CELL
(CELLTYPE "arriagx_lcell_ff")
(INSTANCE ADD_A\[17\])
(DELAY
(ABSOLUTE
(PORT clk (1051:1051:1051) (1051:1051:1051))
(PORT datain (97:97:97) (97:97:97))
(PORT aclr (900:900:900) (900:900:900))
(PORT ena (3156:3156:3156) (3156:3156:3156))
(IOPATH (posedge clk) regout (62:62:62) (62:62:62))
(IOPATH (posedge aclr) regout (136:136:136) (136:136:136))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (47:47:47))
(SETUP ena (posedge clk) (47:47:47))
(HOLD datain (posedge clk) (75:75:75))
(HOLD ena (posedge clk) (75:75:75))
)
)
(CELL
(CELLTYPE "arriagx_asynch_io")
(INSTANCE data\[16\]\~I.inst1)
(DELAY
(ABSOLUTE
(IOPATH padio combout (444:444:444) (444:444:444))
)
)
)
(CELL
(CELLTYPE "arriagx_lcell_ff")
(INSTANCE ADD_A\[16\])
(DELAY
(ABSOLUTE
(PORT clk (1051:1051:1051) (1051:1051:1051))
(PORT adatasdata (3280:3280:3280) (3280:3280:3280))
(PORT aclr (900:900:900) (900:900:900))
(PORT ena (3156:3156:3156) (3156:3156:3156))
(IOPATH (posedge clk) regout (62:62:62) (62:62:62))
(IOPATH (posedge aclr) regout (136:136:136) (136:136:136))
)
)
(TIMINGCHECK
(SETUP adatasdata (posedge clk) (47:47:47))
(SETUP ena (posedge clk) (47:47:47))
(HOLD adatasdata (posedge clk) (75:75:75))
(HOLD ena (posedge clk) (75:75:75))
)
)
(CELL
(CELLTYPE "arriagx_asynch_io")
(INSTANCE data\[15\]\~I.inst1)
(DELAY
(ABSOLUTE
(IOPATH padio combout (500:500:500) (500:500:500))
)
)
)
(CELL
(CELLTYPE "arriagx_lcell_ff")
(INSTANCE ADD_A\[15\])
(DELAY
(ABSOLUTE
(PORT clk (1051:1051:1051) (1051:1051:1051))
(PORT adatasdata (3125:3125:3125) (3125:3125:3125))
(PORT aclr (900:900:900) (900:900:900))
(PORT ena (3156:3156:3156) (3156:3156:3156))
(IOPATH (posedge clk) regout (62:62:62) (62:62:62))
(IOPATH (posedge aclr) regout (136:136:136) (136:136:136))
)
)
(TIMINGCHECK
(SETUP adatasdata (posedge clk) (47:47:47))
(SETUP ena (posedge clk) (47:47:47))
(HOLD adatasdata (posedge clk) (75:75:75))
(HOLD ena (posedge clk) (75:75:75))
)
)
(CELL
(CELLTYPE "arriagx_asynch_io")
(INSTANCE data\[14\]\~I.inst1)
(DELAY
(ABSOLUTE
(IOPATH padio combout (454:454:454) (454:454:454))
)
)
)
(CELL
(CELLTYPE "arriagx_lcell_comb")
(INSTANCE ADD_A\[14\]\~feeder)
(DELAY
(ABSOLUTE
(PORT dataf (2759:2759:2759) (2759:2759:2759))
(IOPATH dataf combout (18:18:18) (18:18:18))
)
)
)
(CELL
(CELLTYPE "arriagx_lcell_ff")
(INSTANCE ADD_A\[14\])
(DELAY
(ABSOLUTE
(PORT clk (1051:1051:1051) (1051:1051:1051))
(PORT datain (97:97:97) (97:97:97))
(PORT aclr (900:900:900) (900:900:900))
(PORT ena (3156:3156:3156) (3156:3156:3156))
(IOPATH (posedge clk) regout (62:62:62) (62:62:62))
(IOPATH (posedge aclr) regout (136:136:136) (136:136:136))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (47:47:47))
(SETUP ena (posedge clk) (47:47:47))
(HOLD datain (posedge clk) (75:75:75))
(HOLD ena (posedge clk) (75:75:75))
)
)
(CELL
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