cordic.fit.qmsg

cordic算法的fpga的实现 采用altera芯片

{ "Info" "ITDC_FITTER_TIMING_ENGINE" "TimeQuest " "Info: Fitter is using the TimeQuest Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "cordic.sdc " "Critical Warning: SDC file not found: 'cordic.sdc'. An SDC file is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the compiler will not properly optimize the design" {  } {  } 1 0 "SDC file not found: '%1!s!'. An SDC file is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the compiler will not properly optimize the design" 0 0 "" 0}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Info: Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -waveform \{0.000 0.500\} -name clk clk " "Info: create_clock -period 1.000 -waveform \{0.000 0.500\} -name clk clk" {  } {  } 0 0 "%1!s!" 0 0 "" 0}  } {  } 0 0 "%1!s!" 0 0 "" 0}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN N20 (CLK3p, Input)) " "Info: Automatically promoted node clk (placed in PIN N20 (CLK3p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/72/quartus/bin/pin_planner.ppl" { clk } } } { "cordic.v" "" { Text "C:/altera/cordic/cordic.v" 26 -1 0 } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_n (placed in PIN M20 (CLK1p, Input)) " "Info: Automatically promoted node rst_n (placed in PIN M20 (CLK1p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G1 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/72/quartus/bin/pin_planner.ppl" { rst_n } } } { "cordic.v" "" { Text "C:/altera/cordic/cordic.v" 27 -1 0 } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_n } "NODE_NAME" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_n } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}