cordic.hier_info

cordic算法的fpga的实现 采用altera芯片

rst_n => x2[3].ACLR
rst_n => x2[4].ACLR
rst_n => x2[5].ACLR
rst_n => x2[6].ACLR
rst_n => x2[7].ACLR
rst_n => z1[0].ACLR
rst_n => z1[1].ACLR
rst_n => z1[2].ACLR
rst_n => z1[3].ACLR
rst_n => z1[4].ACLR
rst_n => z1[5].ACLR
rst_n => z1[6].ACLR
rst_n => z1[7].ACLR
rst_n => y1[0].ACLR
rst_n => y1[1].ACLR
rst_n => y1[2].ACLR
rst_n => y1[3].ACLR
rst_n => y1[4].ACLR
rst_n => y1[5].ACLR
rst_n => y1[6].ACLR
rst_n => y1[7].ACLR
rst_n => x1[0].ACLR
rst_n => x1[1].ACLR
rst_n => x1[2].ACLR
rst_n => x1[3].ACLR
rst_n => x1[4].ACLR
rst_n => x1[5].ACLR
rst_n => x1[6].ACLR
rst_n => x1[7].ACLR
rst_n => z0[0].ACLR
rst_n => z0[1].ACLR
rst_n => z0[2].ACLR
rst_n => z0[3].ACLR
rst_n => z0[4].ACLR
rst_n => z0[5].ACLR
rst_n => z0[6].ACLR
rst_n => z0[7].ACLR
rst_n => y0[0].ACLR
rst_n => y0[1].ACLR
rst_n => y0[2].ACLR
rst_n => y0[3].ACLR
rst_n => y0[4].ACLR
rst_n => y0[5].ACLR
rst_n => y0[6].ACLR
rst_n => y0[7].ACLR
rst_n => x0[0].ACLR
rst_n => x0[1].ACLR
rst_n => x0[2].ACLR
rst_n => x0[3].ACLR
rst_n => x0[4].ACLR
rst_n => x0[5].ACLR
rst_n => x0[6].ACLR
rst_n => x0[7].ACLR
rst_n => phase_in_reg[0].ACLR
rst_n => phase_in_reg[1].ACLR
rst_n => phase_in_reg[2].ACLR
rst_n => phase_in_reg[3].ACLR
rst_n => phase_in_reg[4].ACLR
rst_n => phase_in_reg[5].ACLR
rst_n => phase_in_reg[6].ACLR
rst_n => phase_in_reg[7].ACLR
rst_n => sin_out[7]~reg0.ACLR
rst_n => sin_out[6]~reg0.ACLR
rst_n => sin_out[5]~reg0.ACLR
rst_n => sin_out[4]~reg0.ACLR
rst_n => sin_out[3]~reg0.ACLR
rst_n => sin_out[2]~reg0.ACLR
rst_n => sin_out[1]~reg0.ACLR
rst_n => sin_out[0]~reg0.ACLR
rst_n => cos_out[7]~reg0.ACLR
rst_n => cos_out[6]~reg0.ACLR
rst_n => cos_out[5]~reg0.ACLR
rst_n => cos_out[4]~reg0.ACLR
rst_n => cos_out[3]~reg0.ACLR
rst_n => cos_out[2]~reg0.ACLR
rst_n => cos_out[1]~reg0.ACLR
rst_n => cos_out[0]~reg0.ACLR
rst_n => eps[7]~reg0.ACLR
rst_n => eps[6]~reg0.ACLR
rst_n => eps[5]~reg0.ACLR
rst_n => eps[4]~reg0.ACLR
rst_n => eps[3]~reg0.ACLR
rst_n => eps[2]~reg0.ACLR
rst_n => eps[1]~reg0.ACLR
rst_n => eps[0]~reg0.ACLR
ena => phase_in_reg[7].ENA
ena => phase_in_reg[6].ENA
ena => phase_in_reg[5].ENA
ena => phase_in_reg[4].ENA
ena => phase_in_reg[3].ENA
ena => phase_in_reg[2].ENA
ena => phase_in_reg[1].ENA
ena => phase_in_reg[0].ENA
ena => x0[7].ENA
ena => x0[6].ENA
ena => x0[5].ENA
ena => x0[4].ENA
ena => x0[3].ENA
ena => x0[2].ENA
ena => x0[1].ENA
ena => x0[0].ENA
ena => y0[7].ENA
ena => y0[6].ENA
ena => y0[5].ENA
ena => y0[4].ENA
ena => y0[3].ENA
ena => y0[2].ENA
ena => y0[1].ENA
ena => y0[0].ENA
ena => z0[7].ENA
ena => z0[6].ENA
ena => z0[5].ENA
ena => z0[4].ENA
ena => z0[3].ENA
ena => z0[2].ENA
ena => z0[1].ENA
ena => z0[0].ENA
ena => x1[7].ENA
ena => x1[6].ENA
ena => x1[5].ENA
ena => x1[4].ENA
ena => x1[3].ENA
ena => x1[2].ENA
ena => x1[1].ENA
ena => x1[0].ENA
ena => y1[7].ENA
ena => y1[6].ENA
ena => y1[5].ENA
ena => y1[4].ENA
ena => y1[3].ENA
ena => y1[2].ENA
ena => y1[1].ENA
ena => y1[0].ENA
ena => z1[7].ENA
ena => z1[6].ENA
ena => z1[5].ENA
ena => z1[4].ENA
ena => z1[3].ENA
ena => z1[2].ENA
ena => z1[1].ENA
ena => z1[0].ENA
ena => x2[7].ENA
ena => x2[6].ENA
ena => x2[5].ENA
ena => x2[4].ENA
ena => x2[3].ENA
ena => x2[2].ENA
ena => x2[1].ENA
ena => x2[0].ENA
ena => y2[7].ENA
ena => y2[6].ENA
ena => y2[5].ENA
ena => y2[4].ENA
ena => y2[3].ENA
ena => y2[2].ENA
ena => y2[1].ENA
ena => y2[0].ENA
ena => z2[7].ENA
ena => z2[6].ENA
ena => z2[5].ENA
ena => z2[4].ENA
ena => z2[3].ENA
ena => z2[2].ENA
ena => z2[1].ENA
ena => z2[0].ENA
ena => x3[7].ENA
ena => x3[6].ENA
ena => x3[5].ENA
ena => x3[4].ENA
ena => x3[3].ENA
ena => x3[2].ENA
ena => x3[1].ENA
ena => x3[0].ENA
ena => y3[7].ENA
ena => y3[6].ENA
ena => y3[5].ENA
ena => y3[4].ENA
ena => y3[3].ENA
ena => y3[2].ENA
ena => y3[1].ENA
ena => y3[0].ENA
ena => z3[7].ENA
ena => z3[6].ENA
ena => z3[5].ENA
ena => z3[4].ENA
ena => z3[3].ENA
ena => z3[2].ENA
ena => z3[1].ENA
ena => z3[0].ENA
ena => x4[7].ENA
ena => x4[6].ENA
ena => x4[5].ENA
ena => x4[4].ENA
ena => x4[3].ENA
ena => x4[2].ENA
ena => x4[1].ENA
ena => x4[0].ENA
ena => y4[7].ENA
ena => y4[6].ENA
ena => y4[5].ENA
ena => y4[4].ENA
ena => y4[3].ENA
ena => y4[2].ENA
ena => y4[1].ENA
ena => y4[0].ENA
ena => z4[7].ENA
ena => z4[6].ENA
ena => z4[5].ENA
ena => z4[4].ENA
ena => z4[3].ENA
ena => z4[2].ENA
ena => z4[1].ENA
ena => z4[0].ENA
ena => x5[7].ENA
ena => x5[6].ENA
ena => x5[5].ENA
ena => x5[4].ENA
ena => x5[3].ENA
ena => x5[2].ENA
ena => x5[1].ENA
ena => x5[0].ENA
ena => y5[7].ENA
ena => y5[6].ENA
ena => y5[5].ENA
ena => y5[4].ENA
ena => y5[3].ENA
ena => y5[2].ENA
ena => y5[1].ENA
ena => y5[0].ENA
ena => z5[7].ENA
ena => z5[6].ENA
ena => z5[5].ENA
ena => z5[4].ENA
ena => z5[3].ENA
ena => z5[2].ENA
ena => z5[1].ENA
ena => z5[0].ENA
ena => x6[7].ENA
ena => x6[6].ENA
ena => x6[5].ENA
ena => x6[4].ENA
ena => x6[3].ENA
ena => x6[2].ENA
ena => x6[1].ENA
ena => x6[0].ENA
ena => y6[7].ENA
ena => y6[6].ENA
ena => y6[5].ENA
ena => y6[4].ENA
ena => y6[3].ENA
ena => y6[2].ENA
ena => y6[1].ENA
ena => y6[0].ENA
ena => z6[7].ENA
ena => z6[6].ENA
ena => z6[5].ENA
ena => z6[4].ENA
ena => z6[3].ENA
ena => z6[2].ENA
ena => z6[1].ENA
ena => z6[0].ENA
ena => quadrant[7][1].ENA
ena => quadrant[7][0].ENA
ena => quadrant[6][1].ENA
ena => quadrant[6][0].ENA
ena => quadrant[5][1].ENA
ena => quadrant[5][0].ENA
ena => quadrant[4][1].ENA
ena => quadrant[4][0].ENA
ena => quadrant[3][1].ENA
ena => quadrant[3][0].ENA
ena => quadrant[2][1].ENA
ena => quadrant[2][0].ENA
ena => quadrant[1][1].ENA
ena => quadrant[1][0].ENA
ena => quadrant[0][1].ENA
ena => eps[0]~reg0.ENA
ena => quadrant[0][0].ENA
ena => sin_out[7]~reg0.ENA
ena => sin_out[6]~reg0.ENA
ena => sin_out[5]~reg0.ENA
ena => sin_out[4]~reg0.ENA
ena => sin_out[3]~reg0.ENA
ena => sin_out[2]~reg0.ENA
ena => sin_out[1]~reg0.ENA
ena => sin_out[0]~reg0.ENA
ena => cos_out[7]~reg0.ENA
ena => cos_out[6]~reg0.ENA
ena => cos_out[5]~reg0.ENA
ena => cos_out[4]~reg0.ENA
ena => cos_out[3]~reg0.ENA
ena => cos_out[2]~reg0.ENA
ena => cos_out[1]~reg0.ENA
ena => cos_out[0]~reg0.ENA
ena => eps[7]~reg0.ENA
ena => eps[6]~reg0.ENA
ena => eps[5]~reg0.ENA
ena => eps[4]~reg0.ENA
ena => eps[3]~reg0.ENA
ena => eps[2]~reg0.ENA
ena => eps[1]~reg0.ENA
phase_in[0] => phase_in_reg[0].DATAIN
phase_in[1] => phase_in_reg[1].DATAIN
phase_in[2] => phase_in_reg[2].DATAIN
phase_in[3] => phase_in_reg[3].DATAIN
phase_in[4] => phase_in_reg[4].DATAIN
phase_in[5] => phase_in_reg[5].DATAIN
phase_in[6] => Mux1.IN3
phase_in[6] => Mux1.IN4
phase_in[6] => Mux1.IN5
phase_in[6] => Mux0.IN5
phase_in[6] => Add2.IN4
phase_in[6] => Add0.IN4
phase_in[6] => quadrant[0][0].DATAIN
phase_in[7] => Mux1.IN2
phase_in[7] => Mux0.IN3
phase_in[7] => Mux0.IN4
phase_in[7] => Add2.IN3
phase_in[7] => Add1.IN2
phase_in[7] => Add0.IN3
phase_in[7] => quadrant[0][1].DATAIN
sin_out[0] <= sin_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sin_out[1] <= sin_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sin_out[2] <= sin_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sin_out[3] <= sin_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sin_out[4] <= sin_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sin_out[5] <= sin_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sin_out[6] <= sin_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sin_out[7] <= sin_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_out[0] <= cos_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_out[1] <= cos_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_out[2] <= cos_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_out[3] <= cos_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_out[4] <= cos_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_out[5] <= cos_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_out[6] <= cos_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cos_out[7] <= cos_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
eps[0] <= eps[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
eps[1] <= eps[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
eps[2] <= eps[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
eps[3] <= eps[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
eps[4] <= eps[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
eps[5] <= eps[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
eps[6] <= eps[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
eps[7] <= eps[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE