cordic.fit.rpt

cordic算法的fpga的实现 采用altera芯片

Fitter report for cordic
Wed Nov 12 10:12:32 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. I/O Bank Usage
  9. All Package Pins
 10. Output Pin Default Load For Reported TCO
 11. Fitter Resource Utilization by Entity
 12. Delay Chain Summary
 13. Pad To Core Delay Chain Fanout
 14. Control Signals
 15. Global & Other Fast Signals
 16. Non-Global High Fan-Out Signals
 17. Interconnect Usage Summary
 18. LAB Logic Elements
 19. LAB-wide Signals
 20. LAB Signals Sourced
 21. LAB Signals Sourced Out
 22. LAB Distinct Inputs
 23. I/O Rules Summary
 24. I/O Rules Details
 25. I/O Rules Matrix
 26. Fitter Device Options
 27. Operating Settings and Conditions
 28. Advanced Data - General
 29. Advanced Data - Placement Preparation
 30. Advanced Data - Placement
 31. Advanced Data - Routing
 32. Fitter Messages
 33. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------+
; Fitter Summary                                                           ;
+--------------------------------+-----------------------------------------+
; Fitter Status                  ; Successful - Wed Nov 12 10:12:32 2008   ;
; Quartus II Version             ; 7.2 Build 151 09/26/2007 SJ Web Edition ;
; Revision Name                  ; cordic                                  ;
; Top-level Entity Name          ; cordic                                  ;
; Family                         ; Arria GX                                ;
; Device                         ; EP1AGX20CF484C6                         ;
; Timing Models                  ; Final                                   ;
; Logic utilization              ; 1 %                                     ;
;     Combinational ALUTs        ; 136 / 17,264 ( < 1 % )                  ;
;     Dedicated logic registers  ; 156 / 17,264 ( < 1 % )                  ;
; Total registers                ; 156                                     ;
; Total pins                     ; 35 / 255 ( 14 % )                       ;
; Total virtual pins             ; 0                                       ;
; Total block memory bits        ; 0 / 1,229,184 ( 0 % )                   ;
; DSP block 9-bit elements       ; 0 / 80 ( 0 % )                          ;
; Total GXB Receiver Channels    ; 0 / 4 ( 0 % )                           ;
; Total GXB Transmitter Channels ; 0 / 4 ( 0 % )                           ;
; Total PLLs                     ; 0 / 4 ( 0 % )                           ;
; Total DLLs                     ; 0 / 2 ( 0 % )                           ;
+--------------------------------+-----------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                         ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                                ; Setting                        ; Default Value                  ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                                ; AUTO                           ;                                ;
; Use TimeQuest Timing Analyzer                                         ; On                             ; Off                            ;
; Fit Attempts to Skip                                                  ; 0                              ; 0.0                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                   ; 1                              ; 1                              ;
; Router Timing Optimization Level                                      ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                           ; Off                            ; Off                            ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;