📄 cordic.sta.rpt
字号:
; -0.130 ; 0.500 ; 0.630 ; High ; clk ; Rise ; z2[2] ;
; -0.130 ; 0.500 ; 0.630 ; Low ; clk ; Rise ; z2[2] ;
; -0.130 ; 0.500 ; 0.630 ; High ; clk ; Rise ; x2[5] ;
; -0.130 ; 0.500 ; 0.630 ; Low ; clk ; Rise ; x2[5] ;
; -0.130 ; 0.500 ; 0.630 ; High ; clk ; Rise ; y3[5] ;
; -0.130 ; 0.500 ; 0.630 ; Low ; clk ; Rise ; y3[5] ;
; -0.130 ; 0.500 ; 0.630 ; High ; clk ; Rise ; x4[1] ;
; -0.130 ; 0.500 ; 0.630 ; Low ; clk ; Rise ; x4[1] ;
; -0.130 ; 0.500 ; 0.630 ; High ; clk ; Rise ; y4[5] ;
; -0.130 ; 0.500 ; 0.630 ; Low ; clk ; Rise ; y4[5] ;
; -0.130 ; 0.500 ; 0.630 ; High ; clk ; Rise ; y2[6] ;
; -0.130 ; 0.500 ; 0.630 ; Low ; clk ; Rise ; y2[6] ;
; -0.130 ; 0.500 ; 0.630 ; High ; clk ; Rise ; x2[6] ;
; -0.130 ; 0.500 ; 0.630 ; Low ; clk ; Rise ; x2[6] ;
; -0.130 ; 0.500 ; 0.630 ; High ; clk ; Rise ; z1[2] ;
; -0.130 ; 0.500 ; 0.630 ; Low ; clk ; Rise ; z1[2] ;
; -0.130 ; 0.500 ; 0.630 ; High ; clk ; Rise ; y2[4] ;
; -0.130 ; 0.500 ; 0.630 ; Low ; clk ; Rise ; y2[4] ;
; -0.130 ; 0.500 ; 0.630 ; High ; clk ; Rise ; x3[0] ;
; -0.130 ; 0.500 ; 0.630 ; Low ; clk ; Rise ; x3[0] ;
; -0.130 ; 0.500 ; 0.630 ; High ; clk ; Rise ; z5[0] ;
; -0.130 ; 0.500 ; 0.630 ; Low ; clk ; Rise ; z5[0] ;
; -0.130 ; 0.500 ; 0.630 ; High ; clk ; Rise ; z4[0] ;
; -0.130 ; 0.500 ; 0.630 ; Low ; clk ; Rise ; z4[0] ;
; -0.130 ; 0.500 ; 0.630 ; High ; clk ; Rise ; z3[0] ;
; -0.130 ; 0.500 ; 0.630 ; Low ; clk ; Rise ; z3[0] ;
; -0.130 ; 0.500 ; 0.630 ; High ; clk ; Rise ; z5[1] ;
; -0.130 ; 0.500 ; 0.630 ; Low ; clk ; Rise ; z5[1] ;
; -0.130 ; 0.500 ; 0.630 ; High ; clk ; Rise ; y3[4] ;
; -0.130 ; 0.500 ; 0.630 ; Low ; clk ; Rise ; y3[4] ;
; -0.130 ; 0.500 ; 0.630 ; High ; clk ; Rise ; x4[0] ;
; -0.130 ; 0.500 ; 0.630 ; Low ; clk ; Rise ; x4[0] ;
; -0.130 ; 0.500 ; 0.630 ; High ; clk ; Rise ; y4[4] ;
; -0.130 ; 0.500 ; 0.630 ; Low ; clk ; Rise ; y4[4] ;
; -0.130 ; 0.500 ; 0.630 ; High ; clk ; Rise ; x3[1] ;
+--------+--------------+----------------+--------+-------+------------+--------+
+-------------------------------------------------------------------+
; Setup Transfers ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; clk ; clk ; 1268 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+-------------------------------------------------------------------+
; Hold Transfers ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; clk ; clk ; 1268 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
---------------
; Report TCCS ;
---------------
No LVDS transmitter found in design.
---------------
; Report RSKM ;
---------------
No LVDS receiver found in design.
+------------------------------------------------+
; Unconstrained Paths ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 10 ; 10 ;
; Unconstrained Input Port Paths ; 320 ; 320 ;
; Unconstrained Output Ports ; 24 ; 24 ;
; Unconstrained Output Port Paths ; 24 ; 24 ;
+---------------------------------+-------+------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition
Info: Processing started: Wed Nov 12 10:12:51 2008
Info: Command: quartus_sta cordic -c cordic
Info: qsta_default_script.tcl version: 25.0.1.4
Critical Warning: SDC file not found: 'cordic.sdc'. An SDC file is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the compiler will not properly optimize the design
Info: No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info: Deriving Clocks
Info: create_clock -period 1.000 -waveform {0.000 0.500} -name clk clk
Info: Analyzing Slow Model
Critical Warning: Timing requirements not met
Info: Worst-case setup slack is -1.796
Info: Slack End Point TNS Clock
Info: ========= ============= =====================
Info: -1.796 -139.409 clk
Info: Worst-case hold slack is 0.514
Info: Slack End Point TNS Clock
Info: ========= ============= =====================
Info: 0.514 0.000 clk
Info: No recovery paths to report
Info: No removal paths to report
Critical Warning: Found minimum pulse width or period violations. See Report Minimum Pulse Width for details.
Info: Analyzing Fast Model
Info: Started post-fitting delay annotation
Warning: Found 24 output pins without output pin load capacitance assignment
Info: Pin "sin_out[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sin_out[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sin_out[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sin_out[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sin_out[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sin_out[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sin_out[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sin_out[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cos_out[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cos_out[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cos_out[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cos_out[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cos_out[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cos_out[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cos_out[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cos_out[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "eps[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "eps[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "eps[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "eps[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "eps[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "eps[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "eps[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "eps[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Critical Warning: Timing requirements not met
Info: Worst-case setup slack is -0.128
Info: Slack End Point TNS Clock
Info: ========= ============= =====================
Info: -0.128 -1.968 clk
Info: Worst-case hold slack is 0.214
Info: Slack End Point TNS Clock
Info: ========= ============= =====================
Info: 0.214 0.000 clk
Info: No recovery paths to report
Info: No removal paths to report
Critical Warning: Found minimum pulse width or period violations. See Report Minimum Pulse Width for details.
Warning: Advanced I/O Timing is not enabled
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings
Info: Allocated 159 megabytes of memory during processing
Info: Processing ended: Wed Nov 12 10:12:54 2008
Info: Elapsed time: 00:00:03
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -