cordic.fit.summary

cordic算法的fpga的实现 采用altera芯片

Fitter Status : Successful - Wed Nov 12 10:12:32 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Web Edition
Revision Name : cordic
Top-level Entity Name : cordic
Family : Arria GX
Device : EP1AGX20CF484C6
Timing Models : Final
Logic utilization : 1 %
    Combinational ALUTs : 136 / 17,264 ( < 1 % )
    Dedicated logic registers : 156 / 17,264 ( < 1 % )
Total registers : 156
Total pins : 35 / 255 ( 14 % )
Total virtual pins : 0
Total block memory bits : 0 / 1,229,184 ( 0 % )
DSP block 9-bit elements : 0 / 80 ( 0 % )
Total GXB Receiver Channels : 0 / 4 ( 0 % )
Total GXB Transmitter Channels : 0 / 4 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )