prev_cmp_dds.fit.qmsg

来自「dds算法的fpga实现 altera 根据不同设置」· QMSG 代码 · 共 33 行 · 第 1/5 页

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.771 ns register register " "Info: Estimated most critical path is register to register delay of 3.771 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ADD_A\[0\] 1 REG LAB_X15_Y6 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y6; Fanout = 2; REG Node = 'ADD_A\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ADD_A[0] } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.664 ns) + CELL(0.393 ns) 1.057 ns ADD_B\[0\]~1779 2 COMB LAB_X14_Y6 2 " "Info: 2: + IC(0.664 ns) + CELL(0.393 ns) = 1.057 ns; Loc. = LAB_X14_Y6; Fanout = 2; COMB Node = 'ADD_B\[0\]~1779'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.057 ns" { ADD_A[0] ADD_B[0]~1779 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.128 ns ADD_B\[1\]~1781 3 COMB LAB_X14_Y6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 1.128 ns; Loc. = LAB_X14_Y6; Fanout = 2; COMB Node = 'ADD_B\[1\]~1781'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[0]~1779 ADD_B[1]~1781 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.199 ns ADD_B\[2\]~1783 4 COMB LAB_X14_Y6 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.199 ns; Loc. = LAB_X14_Y6; Fanout = 2; COMB Node = 'ADD_B\[2\]~1783'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[1]~1781 ADD_B[2]~1783 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.270 ns ADD_B\[3\]~1785 5 COMB LAB_X14_Y6 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.270 ns; Loc. = LAB_X14_Y6; Fanout = 2; COMB Node = 'ADD_B\[3\]~1785'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[2]~1783 ADD_B[3]~1785 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.341 ns ADD_B\[4\]~1787 6 COMB LAB_X14_Y6 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.341 ns; Loc. = LAB_X14_Y6; Fanout = 2; COMB Node = 'A