dds.map.qmsg

dds算法的fpga实现 altera 根据不同设置

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Web Edition " "Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 28 15:52:50 2008 " "Info: Processing started: Fri Nov 28 15:52:50 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dds -c dds " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dds -c dds" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_sine.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file rom_sine.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_sine " "Info: Found entity 1: rom_sine" {  } { { "rom_sine.v" "" { Text "C:/altera/dds/rom_sine.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_cose.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file rom_cose.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom_cose " "Info: Found entity 1: rom_cose" {  } { { "rom_cose.v" "" { Text "C:/altera/dds/rom_cose.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dds.v" { { "Info" "ISGN_ENTITY_NAME" "1 dds " "Info: Found entity 1: dds" {  } { { "dds.v" "" { Text "C:/altera/dds/dds.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test_dds.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file test_dds.v" { { "Info" "ISGN_ENTITY_NAME" "1 test_dds " "Info: Found entity 1: test_dds" {  } { { "test_dds.v" "" { Text "C:/altera/dds/test_dds.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dds " "Info: Elaborating entity \"dds\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom_cose rom_cose:cose1 " "Info: Elaborating entity \"rom_cose\" for hierarchy \"rom_cose:cose1\"" {  } { { "dds.v" "cose1" { Text "C:/altera/dds/dds.v" 80 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom_cose:cose1\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"rom_cose:cose1\|altsyncram:altsyncram_component\"" {  } { { "rom_cose.v" "altsyncram_component" { Text "C:/altera/dds/rom_cose.v" 74 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "rom_cose:cose1\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"rom_cose:cose1\|altsyncram:altsyncram_component\"" {  } { { "rom_cose.v" "" { Text "C:/altera/dds/rom_cose.v" 74 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_2571.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_2571.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_2571 " "Info: Found entity 1: altsyncram_2571" {  } { { "db/altsyncram_2571.tdf" "" { Text "C:/altera/dds/db/altsyncram_2571.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_2571 rom_cose:cose1\|altsyncram:altsyncram_component\|altsyncram_2571:auto_generated " "Info: Elaborating entity \"altsyncram_2571\" for hierarchy \"rom_cose:cose1\|altsyncram:altsyncram_component\|altsyncram_2571:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom_sine rom_sine:sine1 " "Info: Elaborating entity \"rom_sine\" for hierarchy \"rom_sine:sine1\"" {  } { { "dds.v" "sine1" { Text "C:/altera/dds/dds.v" 85 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom_sine:sine1\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"rom_sine:sine1\|altsyncram:altsyncram_component\"" {  } { { "rom_sine.v" "altsyncram_component" { Text "C:/altera/dds/rom_sine.v" 74 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "rom_sine:sine1\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"rom_sine:sine1\|altsyncram:altsyncram_component\"" {  } { { "rom_sine.v" "" { Text "C:/altera/dds/rom_sine.v" 74 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_7571.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_7571.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_7571 " "Info: Found entity 1: altsyncram_7571" {  } { { "db/altsyncram_7571.tdf" "" { Text "C:/altera/dds/db/altsyncram_7571.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_7571 rom_sine:sine1\|altsyncram:altsyncram_component\|altsyncram_7571:auto_generated " "Info: Elaborating entity \"altsyncram_7571\" for hierarchy \"rom_sine:sine1\|altsyncram:altsyncram_component\|altsyncram_7571:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "196 " "Info: Implemented 196 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "36 " "Info: Implemented 36 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "32 " "Info: Implemented 32 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "96 " "Info: Implemented 96 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_RAMS" "32 " "Info: Implemented 32 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "152 " "Info: Allocated 152 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 28 15:52:56 2008 " "Info: Processing ended: Fri Nov 28 15:52:56 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}