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📄 dds.tan.qmsg

📁 dds算法的fpga实现 altera 根据不同设置
💻 QMSG
📖 第 1 页 / 共 4 页
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "dds.v" "" { Text "C:/altera/dds/dds.v" 25 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register ADD_B\[0\] register ADD_B\[31\] 248.08 MHz 4.031 ns Internal " "Info: Clock \"clk\" has Internal fmax of 248.08 MHz between source register \"ADD_B\[0\]\" and destination register \"ADD_B\[31\]\" (period= 4.031 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.829 ns + Longest register register " "Info: + Longest register to register delay is 3.829 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ADD_B\[0\] 1 REG LCFF_X14_Y6_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y6_N1; Fanout = 2; REG Node = 'ADD_B\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ADD_B[0] } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.540 ns) + CELL(0.414 ns) 0.954 ns ADD_B\[0\]~1779 2 COMB LCCOMB_X14_Y6_N0 2 " "Info: 2: + IC(0.540 ns) + CELL(0.414 ns) = 0.954 ns; Loc. = LCCOMB_X14_Y6_N0; Fanout = 2; COMB Node = 'ADD_B\[0\]~1779'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.954 ns" { ADD_B[0] ADD_B[0]~1779 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.025 ns ADD_B\[1\]~1781 3 COMB LCCOMB_X14_Y6_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 1.025 ns; Loc. = LCCOMB_X14_Y6_N2; Fanout = 2; COMB Node = 'ADD_B\[1\]~1781'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[0]~1779 ADD_B[1]~1781 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.096 ns ADD_B\[2\]~1783 4 COMB LCCOMB_X14_Y6_N4 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.096 ns; Loc. = LCCOMB_X14_Y6_N4; Fanout = 2; COMB Node = 'ADD_B\[2\]~1783'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[1]~1781 ADD_B[2]~1783 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.167 ns ADD_B\[3\]~1785 5 COMB LCCOMB_X14_Y6_N6 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.167 ns; Loc. = LCCOMB_X14_Y6_N6; Fanout = 2; COMB Node = 'ADD_B\[3\]~1785'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[2]~1783 ADD_B[3]~1785 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.238 ns ADD_B\[4\]~1787 6 COMB LCCOMB_X14_Y6_N8 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.238 ns; Loc. = LCCOMB_X14_Y6_N8; Fanout = 2; COMB Node = 'ADD_B\[4\]~1787'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[3]~1785 ADD_B[4]~1787 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.309 ns ADD_B\[5\]~1789 7 COMB LCCOMB_X14_Y6_N10 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.309 ns; Loc. = LCCOMB_X14_Y6_N10; Fanout = 2; COMB Node = 'ADD_B\[5\]~1789'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[4]~1787 ADD_B[5]~1789 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.380 ns ADD_B\[6\]~1791 8 COMB LCCOMB_X14_Y6_N12 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.380 ns; Loc. = LCCOMB_X14_Y6_N12; Fanout = 2; COMB Node = 'ADD_B\[6\]~1791'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[5]~1789 ADD_B[6]~1791 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 1.539 ns ADD_B\[7\]~1793 9 COMB LCCOMB_X14_Y6_N14 2 " "Info: 9: + IC(0.000 ns) + CELL(0.159 ns) = 1.539 ns; Loc. = LCCOMB_X14_Y6_N14; Fanout = 2; COMB Node = 'ADD_B\[7\]~1793'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.159 ns" { ADD_B[6]~1791 ADD_B[7]~1793 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.610 ns ADD_B\[8\]~1795 10 COMB LCCOMB_X14_Y6_N16 2 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 1.610 ns; Loc. = LCCOMB_X14_Y6_N16; Fanout = 2; COMB Node = 'ADD_B\[8\]~1795'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[7]~1793 ADD_B[8]~1795 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.681 ns ADD_B\[9\]~1797 11 COMB LCCOMB_X14_Y6_N18 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 1.681 ns; Loc. = LCCOMB_X14_Y6_N18; Fanout = 2; COMB Node = 'ADD_B\[9\]~1797'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[8]~1795 ADD_B[9]~1797 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.752 ns ADD_B\[10\]~1799 12 COMB LCCOMB_X14_Y6_N20 2 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 1.752 ns; Loc. = LCCOMB_X14_Y6_N20; Fanout = 2; COMB Node = 'ADD_B\[10\]~1799'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[9]~1797 ADD_B[10]~1799 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.823 ns ADD_B\[11\]~1801 13 COMB LCCOMB_X14_Y6_N22 2 " "Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 1.823 ns; Loc. = LCCOMB_X14_Y6_N22; Fanout = 2; COMB Node = 'ADD_B\[11\]~1801'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[10]~1799 ADD_B[11]~1801 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.894 ns ADD_B\[12\]~1803 14 COMB LCCOMB_X14_Y6_N24 2 " "Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 1.894 ns; Loc. = LCCOMB_X14_Y6_N24; Fanout = 2; COMB Node = 'ADD_B\[12\]~1803'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[11]~1801 ADD_B[12]~1803 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.965 ns ADD_B\[13\]~1805 15 COMB LCCOMB_X14_Y6_N26 2 " "Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 1.965 ns; Loc. = LCCOMB_X14_Y6_N26; Fanout = 2; COMB Node = 'ADD_B\[13\]~1805'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[12]~1803 ADD_B[13]~1805 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.036 ns ADD_B\[14\]~1807 16 COMB LCCOMB_X14_Y6_N28 2 " "Info: 16: + IC(0.000 ns) + CELL(0.071 ns) = 2.036 ns; Loc. = LCCOMB_X14_Y6_N28; Fanout = 2; COMB Node = 'ADD_B\[14\]~1807'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[13]~1805 ADD_B[14]~1807 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.146 ns) 2.182 ns ADD_B\[15\]~1809 17 COMB LCCOMB_X14_Y6_N30 2 " "Info: 17: + IC(0.000 ns) + CELL(0.146 ns) = 2.182 ns; Loc. = LCCOMB_X14_Y6_N30; Fanout = 2; COMB Node = 'ADD_B\[15\]~1809'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.146 ns" { ADD_B[14]~1807 ADD_B[15]~1809 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.253 ns ADD_B\[16\]~1811 18 COMB LCCOMB_X14_Y5_N0 2 " "Info: 18: + IC(0.000 ns) + CELL(0.071 ns) = 2.253 ns; Loc. = LCCOMB_X14_Y5_N0; Fanout = 2; COMB Node = 'ADD_B\[16\]~1811'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[15]~1809 ADD_B[16]~1811 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.324 ns ADD_B\[17\]~1813 19 COMB LCCOMB_X14_Y5_N2 2 " "Info: 19: + IC(0.000 ns) + CELL(0.071 ns) = 2.324 ns; Loc. = LCCOMB_X14_Y5_N2; Fanout = 2; COMB Node = 'ADD_B\[17\]~1813'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[16]~1811 ADD_B[17]~1813 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.395 ns ADD_B\[18\]~1815 20 COMB LCCOMB_X14_Y5_N4 2 " "Info: 20: + IC(0.000 ns) + CELL(0.071 ns) = 2.395 ns; Loc. = LCCOMB_X14_Y5_N4; Fanout = 2; COMB Node = 'ADD_B\[18\]~1815'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[17]~1813 ADD_B[18]~1815 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.466 ns ADD_B\[19\]~1817 21 COMB LCCOMB_X14_Y5_N6 2 " "Info: 21: + IC(0.000 ns) + CELL(0.071 ns) = 2.466 ns; Loc. = LCCOMB_X14_Y5_N6; Fanout = 2; COMB Node = 'ADD_B\[19\]~1817'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[18]~1815 ADD_B[19]~1817 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.537 ns ADD_B\[20\]~1819 22 COMB LCCOMB_X14_Y5_N8 2 " "Info: 22: + IC(0.000 ns) + CELL(0.071 ns) = 2.537 ns; Loc. = LCCOMB_X14_Y5_N8; Fanout = 2; COMB Node = 'ADD_B\[20\]~1819'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[19]~1817 ADD_B[20]~1819 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.608 ns ADD_B\[21\]~1821 23 COMB LCCOMB_X14_Y5_N10 2 " "Info: 23: + IC(0.000 ns) + CELL(0.071 ns) = 2.608 ns; Loc. = LCCOMB_X14_Y5_N10; Fanout = 2; COMB Node = 'ADD_B\[21\]~1821'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[20]~1819 ADD_B[21]~1821 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.679 ns ADD_B\[22\]~1823 24 COMB LCCOMB_X14_Y5_N12 2 " "Info: 24: + IC(0.000 ns) + CELL(0.071 ns) = 2.679 ns; Loc. = LCCOMB_X14_Y5_N12; Fanout = 2; COMB Node = 'ADD_B\[22\]~1823'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[21]~1821 ADD_B[22]~1823 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 2.838 ns ADD_B\[23\]~1825 25 COMB LCCOMB_X14_Y5_N14 2 " "Info: 25: + IC(0.000 ns) + CELL(0.159 ns) = 2.838 ns; Loc. = LCCOMB_X14_Y5_N14; Fanout = 2; COMB Node = 'ADD_B\[23\]~1825'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.159 ns" { ADD_B[22]~1823 ADD_B[23]~1825 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.909 ns ADD_B\[24\]~1827 26 COMB LCCOMB_X14_Y5_N16 2 " "Info: 26: + IC(0.000 ns) + CELL(0.071 ns) = 2.909 ns; Loc. = LCCOMB_X14_Y5_N16; Fanout = 2; COMB Node = 'ADD_B\[24\]~1827'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[23]~1825 ADD_B[24]~1827 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.980 ns ADD_B\[25\]~1829 27 COMB LCCOMB_X14_Y5_N18 2 " "Info: 27: + IC(0.000 ns) + CELL(0.071 ns) = 2.980 ns; Loc. = LCCOMB_X14_Y5_N18; Fanout = 2; COMB Node = 'ADD_B\[25\]~1829'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[24]~1827 ADD_B[25]~1829 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.051 ns ADD_B\[26\]~1831 28 COMB LCCOMB_X14_Y5_N20 2 " "Info: 28: + IC(0.000 ns) + CELL(0.071 ns) = 3.051 ns; Loc. = LCCOMB_X14_Y5_N20; Fanout = 2; COMB Node = 'ADD_B\[26\]~1831'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[25]~1829 ADD_B[26]~1831 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.122 ns ADD_B\[27\]~1833 29 COMB LCCOMB_X14_Y5_N22 2 " "Info: 29: + IC(0.000 ns) + CELL(0.071 ns) = 3.122 ns; Loc. = LCCOMB_X14_Y5_N22; Fanout = 2; COMB Node = 'ADD_B\[27\]~1833'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[26]~1831 ADD_B[27]~1833 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.193 ns ADD_B\[28\]~1835 30 COMB LCCOMB_X14_Y5_N24 2 " "Info: 30: + IC(0.000 ns) + CELL(0.071 ns) = 3.193 ns; Loc. = LCCOMB_X14_Y5_N24; Fanout = 2; COMB Node = 'ADD_B\[28\]~1835'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[27]~1833 ADD_B[28]~1835 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.264 ns ADD_B\[29\]~1837 31 COMB LCCOMB_X14_Y5_N26 2 " "Info: 31: + IC(0.000 ns) + CELL(0.071 ns) = 3.264 ns; Loc. = LCCOMB_X14_Y5_N26; Fanout = 2; COMB Node = 'ADD_B\[29\]~1837'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[28]~1835 ADD_B[29]~1837 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.335 ns ADD_B\[30\]~1839 32 COMB LCCOMB_X14_Y5_N28 1 " "Info: 32: + IC(0.000 ns) + CELL(0.071 ns) = 3.335 ns; Loc. = LCCOMB_X14_Y5_N28; Fanout = 1; COMB Node = 'ADD_B\[30\]~1839'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { ADD_B[29]~1837 ADD_B[30]~1839 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 3.745 ns ADD_B\[31\]~1840 33 COMB LCCOMB_X14_Y5_N30 1 " "Info: 33: + IC(0.000 ns) + CELL(0.410 ns) = 3.745 ns; Loc. = LCCOMB_X14_Y5_N30; Fanout = 1; COMB Node = 'ADD_B\[31\]~1840'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { ADD_B[30]~1839 ADD_B[31]~1840 } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.829 ns ADD_B\[31\] 34 REG LCFF_X14_Y5_N31 9 " "Info: 34: + IC(0.000 ns) + CELL(0.084 ns) = 3.829 ns; Loc. = LCFF_X14_Y5_N31; Fanout = 9; REG Node = 'ADD_B\[31\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { ADD_B[31]~1840 ADD_B[31] } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.289 ns ( 85.90 % ) " "Info: Total cell delay = 3.289 ns ( 85.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.540 ns ( 14.10 % ) " "Info: Total interconnect delay = 0.540 ns ( 14.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.829 ns" { ADD_B[0] ADD_B[0]~1779 ADD_B[1]~1781 ADD_B[2]~1783 ADD_B[3]~1785 ADD_B[4]~1787 ADD_B[5]~1789 ADD_B[6]~1791 ADD_B[7]~1793 ADD_B[8]~1795 ADD_B[9]~1797 ADD_B[10]~1799 ADD_B[11]~1801 ADD_B[12]~1803 ADD_B[13]~1805 ADD_B[14]~1807 ADD_B[15]~1809 ADD_B[16]~1811 ADD_B[17]~1813 ADD_B[18]~1815 ADD_B[19]~1817 ADD_B[20]~1819 ADD_B[21]~1821 ADD_B[22]~1823 ADD_B[23]~1825 ADD_B[24]~1827 ADD_B[25]~1829 ADD_B[26]~1831 ADD_B[27]~1833 ADD_B[28]~1835 ADD_B[29]~1837 ADD_B[30]~1839 ADD_B[31]~1840 ADD_B[31] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.829 ns" { ADD_B[0] {} ADD_B[0]~1779 {} ADD_B[1]~1781 {} ADD_B[2]~1783 {} ADD_B[3]~1785 {} ADD_B[4]~1787 {} ADD_B[5]~1789 {} ADD_B[6]~1791 {} ADD_B[7]~1793 {} ADD_B[8]~1795 {} ADD_B[9]~1797 {} ADD_B[10]~1799 {} ADD_B[11]~1801 {} ADD_B[12]~1803 {} ADD_B[13]~1805 {} ADD_B[14]~1807 {} ADD_B[15]~1809 {} ADD_B[16]~1811 {} ADD_B[17]~1813 {} ADD_B[18]~1815 {} ADD_B[19]~1817 {} ADD_B[20]~1819 {} ADD_B[21]~1821 {} ADD_B[22]~1823 {} ADD_B[23]~1825 {} ADD_B[24]~1827 {} ADD_B[25]~1829 {} ADD_B[26]~1831 {} ADD_B[27]~1833 {} ADD_B[28]~1835 {} ADD_B[29]~1837 {} ADD_B[30]~1839 {} ADD_B[31]~1840 {} ADD_B[31] {} } { 0.000ns 0.540ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.414ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.146ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.012 ns - Smallest " "Info: - Smallest clock skew is 0.012 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.331 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.331 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_H2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk~clkctrl 2 COMB CLKCTRL_G2 208 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 208; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.693 ns) + CELL(0.537 ns) 2.331 ns ADD_B\[31\] 3 REG LCFF_X14_Y5_N31 9 " "Info: 3: + IC(0.693 ns) + CELL(0.537 ns) = 2.331 ns; Loc. = LCFF_X14_Y5_N31; Fanout = 9; REG Node = 'ADD_B\[31\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.230 ns" { clk~clkctrl ADD_B[31] } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 65.04 % ) " "Info: Total cell delay = 1.516 ns ( 65.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.815 ns ( 34.96 % ) " "Info: Total interconnect delay = 0.815 ns ( 34.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.331 ns" { clk clk~clkctrl ADD_B[31] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.331 ns" { clk {} clk~combout {} clk~clkctrl {} ADD_B[31] {} } { 0.000ns 0.000ns 0.122ns 0.693ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.319 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_H2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk~clkctrl 2 COMB CLKCTRL_G2 208 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 208; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.681 ns) + CELL(0.537 ns) 2.319 ns ADD_B\[0\] 3 REG LCFF_X14_Y6_N1 2 " "Info: 3: + IC(0.681 ns) + CELL(0.537 ns) = 2.319 ns; Loc. = LCFF_X14_Y6_N1; Fanout = 2; REG Node = 'ADD_B\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.218 ns" { clk~clkctrl ADD_B[0] } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 65.37 % ) " "Info: Total cell delay = 1.516 ns ( 65.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.803 ns ( 34.63 % ) " "Info: Total interconnect delay = 0.803 ns ( 34.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.319 ns" { clk clk~clkctrl ADD_B[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.319 ns" { clk {} clk~combout {} clk~clkctrl {} ADD_B[0] {} } { 0.000ns 0.000ns 0.122ns 0.681ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.331 ns" { clk clk~clkctrl ADD_B[31] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.331 ns" { clk {} clk~combout {} clk~clkctrl {} ADD_B[31] {} } { 0.000ns 0.000ns 0.122ns 0.693ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.319 ns" { clk clk~clkctrl ADD_B[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.319 ns" { clk {} clk~combout {} clk~clkctrl {} ADD_B[0] {} } { 0.000ns 0.000ns 0.122ns 0.681ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "dds.v" "" { Text "C:/altera/dds/dds.v" 56 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.829 ns" { ADD_B[0] ADD_B[0]~1779 ADD_B[1]~1781 ADD_B[2]~1783 ADD_B[3]~1785 ADD_B[4]~1787 ADD_B[5]~1789 ADD_B[6]~1791 ADD_B[7]~1793 ADD_B[8]~1795 ADD_B[9]~1797 ADD_B[10]~1799 ADD_B[11]~1801 ADD_B[12]~1803 ADD_B[13]~1805 ADD_B[14]~1807 ADD_B[15]~1809 ADD_B[16]~1811 ADD_B[17]~1813 ADD_B[18]~1815 ADD_B[19]~1817 ADD_B[20]~1819 ADD_B[21]~1821 ADD_B[22]~1823 ADD_B[23]~1825 ADD_B[24]~1827 ADD_B[25]~1829 ADD_B[26]~1831 ADD_B[27]~1833 ADD_B[28]~1835 ADD_B[29]~1837 ADD_B[30]~1839 ADD_B[31]~1840 ADD_B[31] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.829 ns" { ADD_B[0] {} ADD_B[0]~1779 {} ADD_B[1]~1781 {} ADD_B[2]~1783 {} ADD_B[3]~1785 {} ADD_B[4]~1787 {} ADD_B[5]~1789 {} ADD_B[6]~1791 {} ADD_B[7]~1793 {} ADD_B[8]~1795 {} ADD_B[9]~1797 {} ADD_B[10]~1799 {} ADD_B[11]~1801 {} ADD_B[12]~1803 {} ADD_B[13]~1805 {} ADD_B[14]~1807 {} ADD_B[15]~1809 {} ADD_B[16]~1811 {} ADD_B[17]~1813 {} ADD_B[18]~1815 {} ADD_B[19]~1817 {} ADD_B[20]~1819 {} ADD_B[21]~1821 {} ADD_B[22]~1823 {} ADD_B[23]~1825 {} ADD_B[24]~1827 {} ADD_B[25]~1829 {} ADD_B[26]~1831 {} ADD_B[27]~1833 {} ADD_B[28]~1835 {} ADD_B[29]~1837 {} ADD_B[30]~1839 {} ADD_B[31]~1840 {} ADD_B[31] {} } { 0.000ns 0.540ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.414ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.146ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.084ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.331 ns" { clk clk~clkctrl ADD_B[31] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.331 ns" { clk {} clk~combout {} clk~clkctrl {} ADD_B[31] {} } { 0.000ns 0.000ns 0.122ns 0.693ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.319 ns" { clk clk~clkctrl ADD_B[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.319 ns" { clk {} clk~combout {} clk~clkctrl {} ADD_B[0] {} } { 0.000ns 0.000ns 0.122ns 0.681ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "ADD_A\[17\] data\[17\] clk 4.628 ns register " "Info: tsu for register \"ADD_A\[17\]\" (data pin = \"data\[17\]\", clock pin = \"clk\") is 4.628 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.998 ns + Longest pin register " "Info: + Longest pin to register delay is 6.998 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.830 ns) 0.830 ns data\[17\] 1 PIN PIN_G7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_G7; Fanout = 1; PIN Node = 'data\[17\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[17] } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.802 ns) + CELL(0.366 ns) 6.998 ns ADD_A\[17\] 2 REG LCFF_X13_Y6_N29 2 " "Info: 2: + IC(5.802 ns) + CELL(0.366 ns) = 6.998 ns; Loc. = LCFF_X13_Y6_N29; Fanout = 2; REG Node = 'ADD_A\[17\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.168 ns" { data[17] ADD_A[17] } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.196 ns ( 17.09 % ) " "Info: Total cell delay = 1.196 ns ( 17.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.802 ns ( 82.91 % ) " "Info: Total interconnect delay = 5.802 ns ( 82.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.998 ns" { data[17] ADD_A[17] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.998 ns" { data[17] {} data[17]~combout {} ADD_A[17] {} } { 0.000ns 0.000ns 5.802ns } { 0.000ns 0.830ns 0.366ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "dds.v" "" { Text "C:/altera/dds/dds.v" 48 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.334 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.334 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_H2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk~clkctrl 2 COMB CLKCTRL_G2 208 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 208; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.696 ns) + CELL(0.537 ns) 2.334 ns ADD_A\[17\] 3 REG LCFF_X13_Y6_N29 2 " "Info: 3: + IC(0.696 ns) + CELL(0.537 ns) = 2.334 ns; Loc. = LCFF_X13_Y6_N29; Fanout = 2; REG Node = 'ADD_A\[17\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.233 ns" { clk~clkctrl ADD_A[17] } "NODE_NAME" } } { "dds.v" "" { Text "C:/altera/dds/dds.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 64.95 % ) " "Info: Total cell delay = 1.516 ns ( 64.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.818 ns ( 35.05 % ) " "Info: Total interconnect delay = 0.818 ns ( 35.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.334 ns" { clk clk~clkctrl ADD_A[17] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.334 ns" { clk {} clk~combout {} clk~clkctrl {} ADD_A[17] {} } { 0.000ns 0.000ns 0.122ns 0.696ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.998 ns" { data[17] ADD_A[17] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.998 ns" { data[17] {} data[17]~combout {} ADD_A[17] {} } { 0.000ns 0.000ns 5.802ns } { 0.000ns 0.830ns 0.366ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.334 ns" { clk clk~clkctrl ADD_A[17] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.334 ns" { clk {} clk~combout {} clk~clkctrl {} ADD_A[17] {} } { 0.000ns 0.000ns 0.122ns 0.696ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}

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