dds.map.summary

来自「dds算法的fpga实现 altera 根据不同设置」· SUMMARY 代码 · 共 18 行

Analysis & Synthesis Status : Successful - Fri Nov 28 15:52:56 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Web Edition
Revision Name : dds
Top-level Entity Name : dds
Family : Arria GX
Logic utilization : N/A
    Combinational ALUTs : 32
    Dedicated logic registers : 96
Total registers : 96
Total pins : 68
Total virtual pins : 0
Total block memory bits : 32,768
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0
Total GXB Receiver Channels : 0
Total GXB Transmitter Channels : 0