dds.sim.rpt

来自「dds算法的fpga实现 altera 根据不同设置」· RPT 代码 · 共 468 行 · 第 1/5 页

; |dds|sine_DR[9]                                                                                  ; |dds|sine_DR[9]                                                                            ; regout           ;
; |dds|sine_DR[8]                                                                                  ; |dds|sine_DR[8]                                                                            ; regout           ;
; |dds|sine_DR[7]                                                                                  ; |dds|sine_DR[7]                                                                            ; regout           ;
; |dds|sine_DR[6]                                                                                  ; |dds|sine_DR[6]                                                                            ; regout           ;
; |dds|sine_DR[5]                                                                                  ; |dds|sine_DR[5]                                                                            ; regout           ;
; |dds|sine_DR[4]                                                                                  ; |dds|sine_DR[4]                                                                            ; regout           ;
; |dds|sine_DR[3]                                                                                  ; |dds|sine_DR[3]                                                                            ; regout           ;
; |dds|sine_DR[2]                                                                                  ; |dds|sine_DR[2]                                                                            ; regout           ;
; |dds|sine_DR[1]                                                                                  ; |dds|sine_DR[1]                                                                            ; regout           ;
; |dds|sine_DR[0]                                                                                  ; |dds|sine_DR[0]                                                                            ; regout           ;
; |dds|we                                                                                          ; |dds|we                                                                                    ; out              ;
; |dds|clk                                                                                         ; |dds|clk                                                                                   ; out              ;
; |dds|sine[0]                                                                                     ; |dds|sine[0]                                                                               ; pin_out          ;
; |dds|sine[1]                                                                                     ; |dds|sine[1]                                                                               ; pin_out          ;
; |dds|sine[2]                                                                                     ; |dds|sine[2]                                                                               ; pin_out          ;
; |dds|sine[3]                                                                                     ; |dds|sine[3]                                                                               ; pin_out          ;
; |dds|sine[4]                                                                                     ; |dds|sine[4]                                                                               ; pin_out          ;
; |dds|sine[5]                                                                                     ; |dds|sine[5]                                                                               ; pin_out          ;
; |dds|sine[6]                                                                                     ; |dds|sine[6]                                                                               ; pin_out          ;
; |dds|sine[7]                                                                                     ; |dds|sine[7]                                                                               ; pin_out          ;
; |dds|sine[8]                                                                                     ; |dds|sine[8]                                                                               ; pin_out          ;
; |dds|sine[9]                                                                                     ; |dds|sine[9]                                                                               ; pin_out          ;
; |dds|sine[10]                                                                                    ; |dds|sine[10]                                                                              ; pin_out          ;
; |dds|sine[11]                                                                                    ; |dds|sine[11]                                                                              ; pin_out          ;
; |dds|sine[12]                                                                                    ; |dds|sine[12]                                                                              ; pin_out          ;
; |dds|sine[13]                                                                                    ; |dds|sine[13]                                                                              ; pin_out          ;
; |dds|sine[14]                                                                                    ; |dds|sine[14]                                                                              ; pin_out          ;
; |dds|sine[15]                                                                                    ; |dds|sine[15]                                                                              ; pin_out          ;
; |dds|cose[0]                                                                                     ; |dds|cose[0]                                                                               ; pin_out          ;
; |dds|cose[1]                                                                                     ; |dds|cose[1]                                                                               ; pin_out          ;
; |dds|cose[2]                                                                                     ; |dds|cose[2]                                                                               ; pin_out          ;
; |dds|cose[3]                                                                                     ; |dds|cose[3]                                                                               ; pin_out          ;
; |dds|cose[4]                                                                                     ; |dds|cose[4]                                                                               ; pin_out          ;
; |dds|cose[5]                                                                                     ; |dds|cose[5]                                                                               ; pin_out          ;
; |dds|cose[6]                                                                                     ; |dds|cose[6]                                                                               ; pin_out          ;
; |dds|cose[7]                                                                                     ; |dds|cose[7]                                                                               ; pin_out          ;
; |dds|cose[8]                                                                                     ; |dds|cose[8]                                                                               ; pin_out          ;
; |dds|cose[9]                                                                                     ; |dds|cose[9]                                                                               ; pin_out          ;
; |dds|cose[10]                                                                                    ; |dds|cose[10]                                                                              ; pin_out          ;
; |dds|cose[11]                                                                                    ; |dds|cose[11]                                                                              ; pin_out          ;
; |dds|cose[12]                                                                                    ; |dds|cose[12]                                                                              ; pin_out          ;
; |dds|cose[13]                                                                                    ; |dds|cose[13]                                                                              ; pin_out          ;
; |dds|cose[14]                                                                                    ; |dds|cose[14]                                                                              ; pin_out          ;
; |dds|cose[15]                                                                                    ; |dds|cose[15]                                                                              ; pin_out          ;
; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0  ; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[0]  ; portadataout0    ;
; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a1  ; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[1]  ; portadataout0    ;
; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a2  ; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[2]  ; portadataout0    ;
; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a3  ; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[3]  ; portadataout0    ;
; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4  ; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[4]  ; portadataout0    ;
; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a5  ; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[5]  ; portadataout0    ;
; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a6  ; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[6]  ; portadataout0    ;
; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a7  ; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[7]  ; portadataout0    ;
; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a8  ; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[8]  ; portadataout0    ;
; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a9  ; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[9]  ; portadataout0    ;
; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a10 ; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[10] ; portadataout0    ;
; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a11 ; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[11] ; portadataout0    ;
; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a12 ; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[12] ; portadataout0    ;
; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a13 ; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[13] ; portadataout0    ;
; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a14 ; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[14] ; portadataout0    ;
; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a15 ; |dds|rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[15] ; portadataout0    ;
; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a0  ; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[0]  ; portadataout0    ;
; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a1  ; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[1]  ; portadataout0    ;
; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a2  ; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[2]  ; portadataout0    ;
; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a3  ; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[3]  ; portadataout0    ;
; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4  ; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[4]  ; portadataout0    ;
; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a5  ; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[5]  ; portadataout0    ;
; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a6  ; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[6]  ; portadataout0    ;
; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a7  ; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[7]  ; portadataout0    ;
; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a8  ; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[8]  ; portadataout0    ;
; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a9  ; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[9]  ; portadataout0    ;
; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a10 ; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[10] ; portadataout0    ;
; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a11 ; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[11] ; portadataout0    ;
; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a12 ; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[12] ; portadataout0    ;
; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a13 ; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[13] ; portadataout0    ;
; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a14 ; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[14] ; portadataout0    ;
; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a15 ; |dds|rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[15] ; portadataout0    ;
; |dds|Add0~160                                                                                    ; |dds|Add0~160                                                                              ; out0             ;
; |dds|Add0~161                                                                                    ; |dds|Add0~161                                                                              ; out0             ;
; |dds|Add0~162                                                                                    ; |dds|Add0~162                                                                              ; out0             ;
; |dds|Add0~163                                                                                    ; |dds|Add0~163                                                                              ; out0             ;
; |dds|Add0~164                                                                                    ; |dds|Add0~164                                                                              ; out0             ;
; |dds|Add0~167                                                                                    ; |dds|Add0~167                                                                              ; out0             ;
; |dds|Add0~168                                                                                    ; |dds|Add0~168                                                                              ; out0             ;
; |dds|Add0~169                                                                                    ; |dds|Add0~169                                                                              ; out0             ;
; |dds|Add0~170                                                                                    ; |dds|Add0~170                                                                              ; out0             ;
; |dds|Add0~171                                                                                    ; |dds|Add0~171                                                                              ; out0             ;
; |dds|Add0~172                                                                                    ; |dds|Add0~172                                                                              ; out0             ;
; |dds|Add0~173                                                                                    ; |dds|Add0~173                                                                              ; out0             ;
; |dds|Add0~174                                                                                    ; |dds|Add0~174                                                                              ; out0             ;
; |dds|Add0~175                                                                                    ; |dds|Add0~175                                                                              ; out0             ;
; |dds|Add0~176                                                                                    ; |dds|Add0~176                                                                              ; out0             ;
; |dds|Add0~177                                                                                    ; |dds|Add0~177                                                                              ; out0             ;
; |dds|Add0~178                                                                                    ; |dds|Add0~178                                                                              ; out0             ;
; |dds|Add0~179                                                                                    ; |dds|Add0~179                                                                              ; out0             ;