dds_v_fast.sdo

来自「dds算法的fpga实现 altera 根据不同设置」· SDO 代码 · 共 2,148 行 · 第 1/5 页

SDO
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12345
    (CELLTYPE "arriagx_asynch_io")
    (INSTANCE data\[13\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (490:490:490) (490:490:490))
      )
    )
  )
  (CELL
    (CELLTYPE "arriagx_lcell_comb")
    (INSTANCE ADD_A\[13\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT dataf (2966:2966:2966) (2966:2966:2966))
        (IOPATH dataf combout (18:18:18) (18:18:18))
      )
    )
  )
  (CELL
    (CELLTYPE "arriagx_lcell_ff")
    (INSTANCE ADD_A\[13\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1051:1051:1051) (1051:1051:1051))
        (PORT datain (97:97:97) (97:97:97))
        (PORT aclr (900:900:900) (900:900:900))
        (PORT ena (3156:3156:3156) (3156:3156:3156))
        (IOPATH (posedge clk) regout (62:62:62) (62:62:62))
        (IOPATH (posedge aclr) regout (136:136:136) (136:136:136))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (47:47:47))
      (SETUP ena (posedge clk) (47:47:47))
      (HOLD datain (posedge clk) (75:75:75))
      (HOLD ena (posedge clk) (75:75:75))
    )
  )
  (CELL
    (CELLTYPE "arriagx_asynch_io")
    (INSTANCE data\[12\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (470:470:470) (470:470:470))
      )
    )
  )
  (CELL
    (CELLTYPE "arriagx_lcell_comb")
    (INSTANCE ADD_A\[12\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT dataf (2963:2963:2963) (2963:2963:2963))
        (IOPATH dataf combout (18:18:18) (18:18:18))
      )
    )
  )
  (CELL
    (CELLTYPE "arriagx_lcell_ff")
    (INSTANCE ADD_A\[12\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1051:1051:1051) (1051:1051:1051))
        (PORT datain (97:97:97) (97:97:97))
        (PORT aclr (900:900:900) (900:900:900))
        (PORT ena (3156:3156:3156) (3156:3156:3156))
        (IOPATH (posedge clk) regout (62:62:62) (62:62:62))
        (IOPATH (posedge aclr) regout (136:136:136) (136:136:136))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (47:47:47))
      (SETUP ena (posedge clk) (47:47:47))
      (HOLD datain (posedge clk) (75:75:75))
      (HOLD ena (posedge clk) (75:75:75))
    )
  )
  (CELL
    (CELLTYPE "arriagx_asynch_io")
    (INSTANCE data\[11\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (460:460:460) (460:460:460))
      )
    )
  )
  (CELL
    (CELLTYPE "arriagx_lcell_comb")
    (INSTANCE ADD_A\[11\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT dataf (2977:2977:2977) (2977:2977:2977))
        (IOPATH dataf combout (18:18:18) (18:18:18))
      )
    )
  )
  (CELL
    (CELLTYPE "arriagx_lcell_ff")
    (INSTANCE ADD_A\[11\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1051:1051:1051) (1051:1051:1051))
        (PORT datain (97:97:97) (97:97:97))
        (PORT aclr (900:900:900) (900:900:900))
        (PORT ena (3156:3156:3156) (3156:3156:3156))
        (IOPATH (posedge clk) regout (62:62:62) (62:62:62))
        (IOPATH (posedge aclr) regout (136:136:136) (136:136:136))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (47:47:47))
      (SETUP ena (posedge clk) (47:47:47))
      (HOLD datain (posedge clk) (75:75:75))
      (HOLD ena (posedge clk) (75:75:75))
    )
  )
  (CELL
    (CELLTYPE "arriagx_asynch_io")
    (INSTANCE data\[10\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (480:480:480) (480:480:480))
      )
    )
  )
  (CELL
    (CELLTYPE "arriagx_lcell_ff")
    (INSTANCE ADD_A\[10\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1051:1051:1051) (1051:1051:1051))
        (PORT adatasdata (3072:3072:3072) (3072:3072:3072))
        (PORT aclr (900:900:900) (900:900:900))
        (PORT ena (3156:3156:3156) (3156:3156:3156))
        (IOPATH (posedge clk) regout (62:62:62) (62:62:62))
        (IOPATH (posedge aclr) regout (136:136:136) (136:136:136))
      )
    )
    (TIMINGCHECK
      (SETUP adatasdata (posedge clk) (47:47:47))
      (SETUP ena (posedge clk) (47:47:47))
      (HOLD adatasdata (posedge clk) (75:75:75))
      (HOLD ena (posedge clk) (75:75:75))
    )
  )
  (CELL
    (CELLTYPE "arriagx_asynch_io")
    (INSTANCE data\[9\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (454:454:454) (454:454:454))
      )
    )
  )
  (CELL
    (CELLTYPE "arriagx_lcell_comb")
    (INSTANCE ADD_A\[9\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT dataf (2741:2741:2741) (2741:2741:2741))
        (IOPATH dataf combout (18:18:18) (18:18:18))
      )
    )
  )
  (CELL
    (CELLTYPE "arriagx_lcell_ff")
    (INSTANCE ADD_A\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1051:1051:1051) (1051:1051:1051))
        (PORT datain (97:97:97) (97:97:97))
        (PORT aclr (900:900:900) (900:900:900))
        (PORT ena (3156:3156:3156) (3156:3156:3156))
        (IOPATH (posedge clk) regout (62:62:62) (62:62:62))
        (IOPATH (posedge aclr) regout (136:136:136) (136:136:136))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (47:47:47))
      (SETUP ena (posedge clk) (47:47:47))
      (HOLD datain (posedge clk) (75:75:75))
      (HOLD ena (posedge clk) (75:75:75))
    )
  )
  (CELL
    (CELLTYPE "arriagx_asynch_io")
    (INSTANCE data\[8\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (474:474:474) (474:474:474))
      )
    )
  )
  (CELL
    (CELLTYPE "arriagx_lcell_ff")
    (INSTANCE ADD_A\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1051:1051:1051) (1051:1051:1051))
        (PORT adatasdata (2882:2882:2882) (2882:2882:2882))
        (PORT aclr (900:900:900) (900:900:900))
        (PORT ena (3156:3156:3156) (3156:3156:3156))
        (IOPATH (posedge clk) regout (62:62:62) (62:62:62))
        (IOPATH (posedge aclr) regout (136:136:136) (136:136:136))
      )
    )
    (TIMINGCHECK
      (SETUP adatasdata (posedge clk) (47:47:47))
      (SETUP ena (posedge clk) (47:47:47))
      (HOLD adatasdata (posedge clk) (75:75:75))
      (HOLD ena (posedge clk) (75:75:75))
    )
  )
  (CELL
    (CELLTYPE "arriagx_asynch_io")
    (INSTANCE data\[7\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (488:488:488) (488:488:488))
      )
    )
  )
  (CELL
    (CELLTYPE "arriagx_lcell_ff")
    (INSTANCE ADD_A\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1053:1053:1053) (1053:1053:1053))
        (PORT adatasdata (2983:2983:2983) (2983:2983:2983))
        (PORT aclr (902:902:902) (902:902:902))
        (PORT ena (3157:3157:3157) (3157:3157:3157))
        (IOPATH (posedge clk) regout (62:62:62) (62:62:62))
        (IOPATH (posedge aclr) regout (136:136:136) (136:136:136))
      )
    )
    (TIMINGCHECK
      (SETUP adatasdata (posedge clk) (47:47:47))
      (SETUP ena (posedge clk) (47:47:47))
      (HOLD adatasdata (posedge clk) (75:75:75))
      (HOLD ena (posedge clk) (75:75:75))
    )
  )
  (CELL
    (CELLTYPE "arriagx_asynch_io")
    (INSTANCE data\[6\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (444:444:444) (444:444:444))
      )
    )
  )
  (CELL
    (CELLTYPE "arriagx_lcell_ff")
    (INSTANCE ADD_A\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1053:1053:1053) (1053:1053:1053))
        (PORT adatasdata (3135:3135:3135) (3135:3135:3135))
        (PORT aclr (902:902:902) (902:902:902))
        (PORT ena (3157:3157:3157) (3157:3157:3157))
        (IOPATH (posedge clk) regout (62:62:62) (62:62:62))
        (IOPATH (posedge aclr) regout (136:136:136) (136:136:136))
      )
    )
    (TIMINGCHECK
      (SETUP adatasdata (posedge clk) (47:47:47))
      (SETUP ena (posedge clk) (47:47:47))
      (HOLD adatasdata (posedge clk) (75:75:75))
      (HOLD ena (posedge clk) (75:75:75))
    )
  )
  (CELL
    (CELLTYPE "arriagx_asynch_io")
    (INSTANCE data\[5\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (444:444:444) (444:444:444))
      )
    )
  )
  (CELL
    (CELLTYPE "arriagx_lcell_comb")
    (INSTANCE ADD_A\[5\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT dataf (3002:3002:3002) (3002:3002:3002))
        (IOPATH dataf combout (18:18:18) (18:18:18))
      )
    )
  )
  (CELL
    (CELLTYPE "arriagx_lcell_ff")
    (INSTANCE ADD_A\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1053:1053:1053) (1053:1053:1053))
        (PORT datain (97:97:97) (97:97:97))
        (PORT aclr (902:902:902) (902:902:902))
        (PORT ena (3157:3157:3157) (3157:3157:3157))
        (IOPATH (posedge clk) regout (62:62:62) (62:62:62))
        (IOPATH (posedge aclr) regout (136:136:136) (136:136:136))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (47:47:47))
      (SETUP ena (posedge clk) (47:47:47))
      (HOLD datain (posedge clk) (75:75:75))
      (HOLD ena (posedge clk) (75:75:75))
    )
  )
  (CELL
    (CELLTYPE "arriagx_asynch_io")
    (INSTANCE data\[4\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (490:490:490) (490:490:490))
      )
    )
  )
  (CELL
    (CELLTYPE "arriagx_lcell_comb")
    (INSTANCE ADD_A\[4\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT dataf (3111:3111:3111) (3111:3111:3111))
        (IOPATH dataf combout (18:18:18) (18:18:18))
      )
    )
  )
  (CELL
    (CELLTYPE "arriagx_lcell_ff")
    (INSTANCE ADD_A\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1053:1053:1053) (1053:1053:1053))
        (PORT datain (97:97:97) (97:97:97))
        (PORT aclr (902:902:902) (902:902:902))
        (PORT ena (3157:3157:3157) (3157:3157:3157))
        (IOPATH (posedge clk) regout (62:62:62) (62:62:62))
        (IOPATH (posedge aclr) regout (136:136:136) (136:136:136))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (47:47:47))
      (SETUP ena (posedge clk) (47:47:47))
      (HOLD datain (posedge clk) (75:75:75))
      (HOLD ena (posedge clk) (75:75:75))
    )
  )
  (CELL
    (CELLTYPE "arriagx_asynch_io")
    (INSTANCE data\[3\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (454:454:454) (454:454:454))
      )
    )
  )
  (CELL
    (CELLTYPE "arriagx_lcell_comb")
    (INSTANCE ADD_A\[3\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT dataf (2605:2605:2605) (2605:2605:2605))
        (IOPATH dataf combout (18:18:18) (18:18:18))
      )
    )
  )
  (CELL
    (CELLTYPE "arriagx_lcell_ff")
    (INSTANCE ADD_A\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1053:1053:1053) (1053:1053:1053))
        (PORT datain (97:97:97) (97:97:97))
        (PORT aclr (902:902:902) (902:902:902))
        (PORT ena (3157:3157:3157) (3157:3157:3157))
        (IOPATH (posedge clk) regout (62:62:62) (62:62:62))
        (IOPATH (posedge aclr) regout (136:136:136) (136:136:136))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (47:47:47))
      (SETUP ena (posedge clk) (47:47:47))
      (HOLD datain (posedge clk) (75:75:75))
      (HOLD ena (posedge clk) (75:75:75))
    )
  )
  (CELL
    (CELLTYPE "arriagx_asynch_io")
    (INSTANCE data\[2\]\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (490:490:490) (490:490:490))
      )
    )
  )
  (CELL
    (CELLTYPE "arriagx_lcell_comb")
    (INSTANCE ADD_A\[2\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT dataf (3021:3021:3021) (3021:3021:3021))
        (IOPATH dataf combout (18:18:18) (18:18:18))
      )
    )
  )
  (CELL
    (CELLTYPE "arriagx_lcell_ff")
    (INSTANCE ADD_A\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1053:1053:1053) (1053:1053:1053))
        (PORT datain (97:97:97) (97:97:97))
        (PORT aclr (902:902:902) (902:902:902))
        (PORT ena (3157:3157:3157) (3157:3157:3157))
        (IOPATH (posedge clk) regout (62:62:62) (62:62:62))
        (IOPATH (posedge aclr) regout (136:136:136) (136:136:136))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (47:47:47))
      (SETUP ena (posedge clk) (47:47:47))
      (HOLD datain (posedge clk) (75:75:75))
      (HOLD ena (posedge clk) (75:75:75))
    )
  )
  (CELL
    (CELLTYPE "arriagx_asynch_io")
    (INSTANCE data\[1\]\~I.inst1)
12345

dds_v_fast.sdo - 源码说明

本页面展示了「dds算法的fpga实现 altera 根据不同设置」中的 dds_v_fast.sdo 源码文件，采用 SDO 编程语言编写，共 2,148 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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