wf.vhd

来自「全数字fsk调制解调的实现 verilog源码」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity wf is 
port (clk ,rz : in std_logic;
      bitout : out std_logic);
end wf;

architecture wf of wf is
signal pre :std_logic_vector (1 downto 0);
begin
process (clk)
begin
if clk'event and clk='1' then
pre(1)<=pre(0);
pre(0)<=rz;
   if (pre="01") then bitout<='1';
     else bitout<='0';
end if;
end if;
end process;
end wf;