div16.vhd

来自「全数字fsk调制解调的实现 verilog源码」· VHDL 代码 · 共 28 行

LIBRARY ieee;
USE ieee.std_logic_1164.all; 
USE ieee.std_logic_arith.all; 
USE ieee.std_logic_unsigned.all; 
LIBRARY work;

ENTITY div16 IS 
	port
	(
		clk :  IN  STD_LOGIC;
		divout :  OUT  STD_LOGIC
	);
END div16;

ARCHITECTURE bdf_type OF div16 IS 
begin
PROCESS(CLK) 
variable COUNT0:STD_LOGIC_VECTOR(0 TO 3);
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF COUNT0 >= "0000" AND COUNT0 <"1111" 
THEN COUNT0 :=COUNT0+1;
ELSE COUNT0 :="0000";
END IF;
divout<=COUNT0(0);
END IF;
END PROCESS;
end bdf_type;