prev_cmp_2fsk_final.tan.qmsg

全数字fsk调制解调的实现 verilog源码

{ "Info" "ITDB_TH_RESULT" "mx_7821:inst6\|dout\[7\] din\[7\] clk 0.300 ns register " "Info: th for register \"mx_7821:inst6\|dout\[7\]\" (data pin = \"din\[7\]\", clock pin = \"clk\") is 0.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.700 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 5.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 6; CLK Node = 'clk'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "2fsk_final.bdf" "" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { -40 -288 -120 -24 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns div64:inst11\|divout 2 REG LC1_C24 17 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_C24; Fanout = 17; REG Node = 'div64:inst11\|divout'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { clk div64:inst11|divout } "NODE_NAME" } } { "div64.vhd" "" { Text "E:/quartus/program/2fsk_final/div64.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.000 ns) 5.700 ns mx_7821:inst6\|dout\[7\] 3 REG LC7_A1 2 " "Info: 3: + IC(2.800 ns) + CELL(0.000 ns) = 5.700 ns; Loc. = LC7_A1; Fanout = 2; REG Node = 'mx_7821:inst6\|dout\[7\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { div64:inst11|divout mx_7821:inst6|dout[7] } "NODE_NAME" } } { "mx_7821.vhd" "" { Text "E:/quartus/program/2fsk_final/mx_7821.vhd" 28 -1 0 } }  } 0 0 "%4!d!: